T1/E1/J1 SINGLE-CHIP TRANSCEIVER PROVIDES SINGLE APPLICATION DESIGN FOR WORLD-WIDE INTEROPERABILITY
DALLAS, TX-May 30, 2001-The DS2155 combination T1/E1/J1 single-chip transceiver allows true in-system software selection of the T1, E1, or J1 protocol without requiring external relays or switches. The new device contains complete DS1/ISDN–PRI/J1 and E1 (CEPT) PCM-30/ISDN-PRI transceiver functionality including a long-and short-haul line interface; crystal-less jitter attenuator; dual HDLC controllers; internal software-selectable receive and transmit side termination for 75/100/120 ohm T1 and E1 interfaces; two-frame elastic store slip buffers for connection to backplanes up to 16.384 MHz; Interleaving PCM Bus Operation; IEEE 1149.1 JTAG-Boundary Scan; and 3.3V supply with 5V tolerant I/O. Pin-compatible with DS2152/54, DS352/354 & DS552/554 SCTs, the DS2155 is used in global T1/E1/J1 access equipment, routers, CSUs, DSL add/drop muxes, and switches.
Features include:
- Software-selectable RX/TX termination for 75/100/120 ohm T1 and E1 interfaces
- On-chip programmable Bit Error Rate Tester (BERT)
- Programmable output clocks for Fractional T1, E1, H0, and H12 applications
- Synthesized 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output phase-locked to the recovered network clock
- CMI code/decode for optical interface design
- Signaling System 7 support
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