5-TAP SILICON DELAY LINE IN NEW MICRO PACKAGING USES PATENTED TECHNOLOGY TO IMPROVE BOARD-LEVEL SIGNAL TIMING
DALLAS, TX-July 18, 2000-Dallas Semiconductor today announced the DS1100 5-Tap Solid State Delay Line which increases a system's performance speed by allowing system designers to adjust clock phase or signal skew in space-constrained digital systems. Using a new, patented design and manufacturing process, the DS1100 can replace less precise delay lines with superior performance while requiring less power and board space. A single version of the DS1100 guarantees performance to specifications over both commercial and temperature ranges.
Driven by ever-increasing system speeds, board-level signal timing has become critical. Designers can use delay lines to precisely adjust clock phase or signal skew between timing-sensitive circuits. System performance can be optimized through careful manipulation of the references used to clock data and control signals, resulting in improved performance in most digital systems, from memory buses to data acquisition.
Delay lines, once used only as last minute corrections to system timing problems, in recent years have become an indispensable tool in the system designer's tool kit. The idea is to improve performance by optimizing signal timing in different areas of a digital system. John Adams, product manager for the DS1100, said, "In the 1980s, Dallas' DS1000 was a revolutionary solid state replacement to the bulky and complicated delay lines made of discrete components, providing a smaller, more cost-effective and reliable solution. Now, using new patented technology and manufacturing processes, we can take smaller packaging, improved performance and lower cost a step further. Like the DS1000 series, the DS1100 also features five equally spaced taps, or outputs, that reproduce an input logic state after a fixed delay. Although based on new technology, the DS1100 series is backward-compatible with the DS1000 series of parts."
"The DS1100 uses a completely different architecture, which Dallas developed and patented," Adams continued. "The older delay lines were trimmed to specifications using laser fuses. The DS1100 uses a small EEPROM array instead, with several important benefits. We can trim a timing delay after the die has been packaged, which improves accuracy and cuts production time. EEPROM requires less supply current. And we have been able to reduce the package size and cost by using improved, smaller-geometry processes."
Previously, the accuracy of laser-trimmed delay lines was limited by "package shift," which is a timing deviation caused by temperature and voltage variations during the packaging process. The new delays are set by a chain of individual delay elements. Each element converts frequency to voltage, compares it to a voltage reference stored in EEPROM, and adjusts signal timing accordingly. This method cancels any variations in a timing delay caused by temperature or voltage fluctuation; the ultimate accuracy is determined by the components in the reference comparison circuit. Delay times in the DS1100 range from 4 ns to 300 ns, with improved performance over temperature and voltage when compared to the older technology. Improved manufacturing processes allow adherence to these specifications over the industrial temperature range.
The DS1100 is in stock and available now in 5-volt versions and package options of 8-pin DIP, SOIC, and µSOP. Its cost is $1.93 in quantities of 1,000. A 3-volt version is in development.
Dallas Semiconductor manufactures specialty semiconductors focused in three areas: Communications, 1-Wire® and Network Computing, and Mixed Signal. The Company combines proprietary fab and circuit technologies to create innovative products that are sold to over 15,000 customers worldwide. Applications include broadband telecommunications, wireless handsets, cellular base stations, secure Internet communications, networking, servers, data storage and a wide variety of industrial equipment.
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