FIRST 3V, MULTI-TAP DELAY LINE FROM DALLAS SEMICONDUCTOR SIMPLIFIES DESIGNS IN LOW-POWER DIGITAL SYSTEMS
DALLAS, TX-December 5, 2000-Dallas Semiconductor today announced the DS1100L 5-Tap Solid-State Delay Line, the industry's first 5-tap, solid-state delay line for 3-volt applications. Total delays offered are from 20 to 300 ns and tap-to-tap delays from 4 to 60 ns. As timing issues become critical in high-speed designs, this specialized circuit contributes toward higher performance with higher precision, smaller size, and power savings. To date, similar advantages were only available for 5-volt systems; the DS1100L now gives the 3-volt system designer a new and flexible tool.
 Designers use all-silicon timing delay circuits to precisely adjust clock phase or signal skew between different blocks of timing-sensitive circuits. Careful manipulation of the references used to clock data, filter noise and control signals can improve performance in any digital system, from memory buses to data acquisition. However, the most common application for low-voltage timing correction is now in the servers, routers and switches of high-speed digital telecommunications systems.
"Systems designers are moving to lower and lower voltages for one major reason: reduced power consumption," said John Adams, Dallas Semiconductor's marketing manager for delay lines. "The DS1100L uses 30% of the current and less than 20% of the energy when compared to 5-volt parts. Lower over-all power in a design can mean longer battery life or smaller batteries, smaller power supplies, reduced heat, and lower overall operating costs over the life span of a product.
"Further, anything that reduces footprint and volume consumes less board space, making the PC board lighter and simpler. Telecommunications designers are particularly constrained by small space requirements. In the µSOP package, the DS1100L requires only one-fifteenth the footprint of older parts from just a few years back."
Superior timing precision in the DS1100L is based on a new manufacturing process that eliminates post-packaging parameter shifts. A single version maintains specifications over both the commercial and industrial temperature ranges.
Adams said, "Based on EEPROM calibration technology instead of laser-trimming at the wafer level, the DS1100L is more easily and precisely specified and remains more stable than previous generations of delay circuits. With these advantages in a 5-tap delay, the 3-volt system designer has easier, more flexible ways to solve timing problems."
The DS1100L is sampling now and production is expected in early 2001. Package options consist of 8-pin DIPs, 8-pin SOICs, and 8-pin µSOPs. The cost is $2.72 for the DS1100L in the SOIC package in quantities of 1,000.
Dallas Semiconductor manufactures specialty semiconductors focused in three areas: Communications, 1-Wire® and Network Computing, and Mixed Signal. The Company combines proprietary fab and circuit technologies to create innovative products that are sold to over 15,000 customers worldwide. Applications include broadband telecommunications, wireless handsets, cellular base stations, secure Internet communications, networking, servers, data storage and a wide variety of industrial equipment.
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