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Maxim > Solutions > Telecom Line Cards: T1, E1, J1

Single Chip Transceivers: Combination T1, E1, J1

DATA SHEETS
Display Title/Parts Key Advantages
QV  PDF Single/Dual/Quad/Octal TDM-Over-Packet Transport Devices
DS34S101, DS34S102, DS34S104, DS34S108

Smallest, Most Robust, Lowest Cost Choice for Delivering TDM Services Over Pseudowires
QV  PDF High-Precision Clock Generators with Integrated VCXO
MAX9450, MAX9451, MAX9452

First SONET Clock Generator with Integrated VCXO and Holdover for Replacing Expensive VCXOs and External Fail-Safe Logic
QV  PDF Ethernet Mapper with Integrated T1/E1/J1 Transceiver
DS33R11

QV  PDF Single T1/E1/J1 Transceiver
DS26521

Single-Port T1/E1/J1 Transceiver Is a Single-Chip Framer and LIU Combination for T1, E1, and J1 Applications
QV  PDF Quad Ethernet Mapper
DS33Z44

QV  PDF T1/E1/J1/64KCC BITS Element
DS26504

QV  PDF Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
DS33R41

Greatly Simplifies the Design of Applications for Transporting Ethernet Packets Over Up to Four T1 or E1 Lines
QV  PDF DS3/E3 Single-Chip Transceiver
DS3170

QV  PDF 4-Port Cell/Packet Over T1/E1/J1 Transceiver
DS26556

4-Port Cell/Packet Over T1/E1/J1 Single-Chip Transceiver
QV  PDF Quad T1/E1/J1 Transceivers
DS21455, DS21458

Industry's First 4-Port Transceivers to Switch Among All T1, E1, and J1 Standards without External Component Changes
QV  PDF T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface
DS2156, DS2156L, DS2156LN

Industry's First T1/E1/J1 Transceiver for ATM Applications
QV  PDF Quad T1/E1/J1 Transceiver
DS21Q55, DS21Q55N

QV  PDF T1/E1/J1 Single-Chip Transceiver
DS2155

T1/E1/J1 Single-Chip Transceiver Provides Single Application Design for World-Wide Interoperability



Key Specifications:  Clock Generators
Part Number Applications fIN
(MHz)
fIN
(MHz)
fOUT
(MHz)
fOUT
(MHz)
Fixed or Continuous Frequency Output Levels Out-
puts
PLLs Program-
mability
Spread Spectrum Output Jitter
(ps)
VSUPPLY
(V)
Package/Pins
min max min max RMS
MAX9451 
Ethernet
Fibre Channel
GSM
SONET/SDH
UMTS
W-CDMA
0.008 500 15 160 Continuous HSTL 2 1 I2C No 0.8
2.5
3.3
TQFP-EP/32
MAX9450  LVPECL
TQFP-EP/32
MAX9452  LVDS
TQFP-EP/32
See All Clock Generators (27)

Key Specifications:  T/E Carrier & Packetized Products
Part Number Transmission Standard Functions Channels In-to-Out Clocks
(MHz)
VSUPPLY
(V)
EV Kit RoHS Available Package/Pins Smallest Available Pckg.
(mm2)
max w/pins
DS26521  T1/E1/J1 Framer + LIU 1 External Master Clock can be a multiple of 1.544 or 2.048 3.3 Yes See Data Sheet
See Data Sheet/
-
DS33R11 
Ethernet/Serial TDM
T1/E1/J1
Ethernet Mapper 1 1.544 to 4.096 & 8.192 Yes Yes
PBGA/256
729
DS33R41 
Ethernet/Serial TDM
T1/E1/J1
Ethernet Mapper 4 - - Yes
PBGA/400
729
DS26556  T1/E1/J1 Framer + LIU 4 External Master Clock can be a multiple of 1.544 or 2.048 - See Data Sheet
CSBGA/256
289
DS33Z44  Ethernet/Serial TDM Ethernet Mapper 4 - Yes Yes
CSBGA/256
TCBGA/256
-
DS3170  T3/E3 Framer + LIU 1 - Yes Yes
CSBGA/100
121
DS26504 
64kHz Composite Clock - G.703 Level B
64kHz - G.703 II.1 Japanese 64kHz Clock
64kHz Composite Clock - GR378
64kHz - G.703 II.2 Japanese 6312kHz Clock
64kHz Composite Clock - G.703 Level A
T1/E1/J1
BITS Element 1
0.008
0.064
1.544
2.048
6.312
19.44
Yes See Data Sheet
See Data Sheet/
-
DS21455  T1/E1/J1 Framer + LIU 4 - - Yes
PBGA/256
729
DS21458  T1/E1/J1 Framer + LIU 4 - Yes Yes
CSBGA/256
289
DS2156  T1/E1/J1 Framer + LIU 1 External Master Clock can be a multiple of 1.544 or 2.048 Yes Yes
CSBGA/100
LQFP/100
100
DS2155  T1/E1/J1 Framer + LIU 1 - Yes Yes
CSBGA/100
LQFP/100
100
See All T/E Carrier & Packetized Products (102)

Key Specifications:  High-Speed Interconnect (Differential Signaling)
Part Number Signal Type Tx VSUPPLY
(V)
Tx
MAX9450  LVPECL 2
2.5
3.3
See All High-Speed Interconnect (Differential Signaling) (132)

Key Specifications:  TDM-Over-Packet
Part Number T1/E1/Serial Streams T3/E3, STS-1 Serial Ports Mapping Methods PSN Encapsulation Protocols 10/100 MAC Interface Processor Interface Package/Pins Smallest Available Pckg.
(mm2)
RoHS Available
max w/pins
DS34S101  1 1
AAL1
CESoPSN
HDLC
SAToP
Structured
Structured with CAS
TDMoIP
Unstructured
L2TPv3 (IPv4, IPv6)
MEF-8
MPLS
RTP
UDP (IPv4, IPv6)
MII
RMII
SSMII
16-Bit
32-Bit
SPI
CSBGA/256
289 Yes
DS34S102  2
CSBGA/256
289
DS34S104  4
CSBGA/256
289
DS34S108  8
BGA/484
529
See All TDM-Over-Packet (9)



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