ENGLISH 简体中文 日本語 한국어  

    Login | Register 


   
 
Enter keywords or part number    



DS34S132
32-Port TDM-over-Packet IC

Highly Integrated, 32-Port, TDM-over-Packet IC Provides Industry-Leading Clock Recovery for TDM-over-Packet


  QuickView     Technical Documents     Ordering Info     More Information     User Comments (0)     All  
Status
Active: In Production.

Description
ABRIDGED DATA SHEET (PDF, 588kB)
Download this datasheet in PDF formatDownload Request Full Data Sheet
The IETF PWE3 SAToP/CESoPSN/HDLC-compliant DS34S132 provides the interworking functions that are required for translating TDM data streams into and out of TDM-over-Packet (TDMoP) data streams for L2TPv3/IP, UDP/IP, MPLS (MFA-8), and Metro Ethernet (MEF-8) networks while meeting the jitter and wander timing performance that is required by the public network (ITU G.823, G.824, and G.8261). Up to 32 TDM ports can be translated into as many as 256 individually configurable pseudowires (PWs) for transmission over a 100/1000Mbps Ethernet port. Each TDM port's bit rate can vary from 64Kbps to 2.048Mbps to support T1/E1 or slower TDM rates. PW interworking for TDM-based serial HDLC data is also supported. A built-in time-slot assignment (TSA) circuit provides the ability to combine any group of time slots (TS) from a single TDM port into a single PW. The high level of integration provides the perfect solution for high-density applications to minimize cost, board space, and time to market.

Key Features   Applications/Uses
  • 32 Independent TDM Ports with Serial Data, Clock, and Sync (Data = 64Kbps to 2.048Mbps)
  • One 100/1000Mbps (MII/GMII) Ethernet MAC
  • 256 Total PWs, 32 PW per TDM Port, with Any Combination of TDMoP and/or HDLC PWs
  • PSN Protocols: L2TPv3 or UDP Over IP (IPv4 or IPv6), Metro Ethernet (MEF-8), or MPLS (MFA-8)
  • 0, 1, or 2 VLAN Tags (IEEE 802.1Q)
  • Synchronous or Asynchronous TDM Port Timing
    • One Clock Recovery Engine per TDM Port with One Assignable as a Global Reference
    • Supported Clock Recovery Techniques
      • Adaptive Clock Recovery
      • Differential Clock Recovery
      • Absolute and Differential Timestamps
    • Independent Receive and Transmit Interfaces
    • Two Clock Inputs for Direct Transmit Timing
  • For Structured T1/E1, Each TDM Port Includes
    • DS0 TSA Block for any Time Slot to Any PW
    • 32 HDLC/CES Engines (256 Total)
    • With or Without CAS Signaling
  • For Unstructured, each TDM Port Includes
    • One HDLC/SAT Engine (32 Total)
    • Any data rate from 64Kbps to 2.048Mbps
  • 32-Bit or 16-Bit CPU Processor Bus
  • CPU-Based OAM and Signaling
    • UDP-specific "Special" Ethernet Type
    • Inband VCCV ARP
    • MEF OAM
    • Broadcast DA
    • NDP/IPv6
  • DDR SDRAM Interface
  • Low-Power 1.8V Core, 3.3V I/O, 2.5V SDRAM

 
  • HDLC-Encapsulated Data Over PSN
  • TDM Circuit Emulation Over PSN (TDM Leased-Line Services Over PSN, TDM Over BPON/GPON/EPON, TDM Over Cable, TDM Over Wireless, Cellular Backhaul, Multiservice Over Unified PSN)

Key Specifications:  TDM-Over-Packet
Part Number T1/E1/Serial Streams T3/E3, STS-1 Serial Ports Mapping Methods PSN Encapsulation Protocols 10/100 MAC Interface Processor Interface Package/Pins Smallest Available Pckg.
(mm2)
Price
max w/pins See Notes
DS34S132  32 0
CESoPSN
HDLC
SAToP
Structured
Structured with CAS
TDMoIP
Unstructured
L2TPv3 (IPv4, IPv6)
MEF-8
MPLS
UDP (IPv4, IPv6)
GMII
MII
16-Bit
32-Bit
TEPBGA-HS/676
729 $105.60 @1k
See All TDM-Over-Packet (9)

Diagram
DS34S132: Functional Diagram
Functional Diagram

Didn't Find What You Need?
  • Next Day Product Selection Assistance from Applications Engineers
  • Parametric Search
  • Applications Help
  •  QuickView   Technical Documents   Ordering Info   More Information  
     Description 
     Key Features 
     Applications/Uses 
     Key Specifications 
     Diagram 

     Data Sheet 
     Application Notes 
     Design Guides 
     Engineering Journals 
     Reliability Reports 
     Software/Models 
     Evaluation Kits 

     Price and Availability 
     Samples 
     Buy Online 
     Package Information 
     Lead-Free Information 

     Related Products 
     Notes and Comments 
     Evaluation Kits 

    Document Ref.: 19-4750; 2009-07-24
    This page last modified: 2009-07-30


            •         •         •     Privacy Policy     •     Legal Notices

        Copyright © 2009 by Maxim Integrated Products