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MAX3627
+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs

Seven LVDS Outputs and One LVCMOS Output with 0.2psRMS Jitter in a Small 5mm x 5mm Package


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Status
Active: In Production.

Description
FULL DATA SHEET (PDF, 620kB)
Download this datasheet in PDF formatDownload   Send this datasheet to any email addressE-Mail
The MAX3627 is a low-jitter, precision clock generator optimized for network applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) to generate high-frequency clock outputs for Ethernet applications.

Maxim's proprietary PLL design features ultra-low jitter (0.4psRMS) and excellent power-supply noise rejection (PSNR), minimizing design risk for network equipment.

The MAX3627 contains seven LVDS outputs and one LVCMOS output. The output frequencies are selectable among 125MHz, 156.25MHz, and 312.5MHz.

Key Features   Applications/Uses
  • Crystal Oscillator Interface: 25MHz
  • OSC_IN Interface
    • PLL Enabled: 25MHz
    • PLL Disabled: 20MHz to 320MHz
  • Outputs
    • One LVDS Output at 125MHz/156.25MHz/312.5MHz (Selectable with FSELA)
    • Six LVDS Outputs at 125MHz/156.25MHz/312.5MHz (Selectable with FSELB)
    • One LVCMOS Output at 125MHz/156.25MHz (Selectable with FSELB)
  • Low Phase Jitter
    • 0.4psRMS (12kHz to 20MHz)
    • 0.2psRMS (1.875MHz to 20MHz)
  • Excellent PSNR: -64dBc at 156.25MHz with 40mVP-P Supply Noise at 100kHz
  • Operating Temperature Range: 0°C to +70°C

 
  • Ethernet Networking Equipment

Diagram
MAX3627: Typical Operating Circuit
Typical Operating Circuit

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    Document Ref.: 19-4567; Rev 0; 2009-04-29
    This page last modified: 2009-04-29


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