The MAX3629 is a low-jitter precision clock generator optimized for network applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) to generate high-frequency clock outputs for Ethernet applications.
Maxim's proprietary PLL design features ultra-low jitter (0.4psRMS) and excellent power-supply noise rejection (PSNR), minimizing design risk for network equipment.
The MAX3629 contains five LVDS outputs and three LVCMOS outputs. The output frequencies are selectable among 125MHz, 156.25MHz, and 312.5MHz by pin control.
Key Features
Applications/Uses
Crystal Oscillator Interface: 25MHz
OSC_IN Interface:
PLL Enabled: 25MHz
PLL Disabled: 20MHz to 320MHz
Outputs:
One LVDS Output at 125MHz/156.25MHz/312.5MHz (Selectable with FSELA)
Four LVDS Outputs at 125MHz/156.25MHz/312.5MHz (Selectable with FSELB)
Three LVCMOS Outputs at 125MHz/156.25MHz (Selectable with FSELB)
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
Devices:
1-2 of 2
MAX3629
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Status
Package:
TYPE PINS FOOTPRINT
DRAWING CODE/VAR *
Temp
RoHS/Lead-Free? Materials Analysis
MAX3629CTJ+T
Active
Land Pattern: Not Available
0°C to +70°C
See data sheet
MAX3629CTJ+
Active
TQFN;32 pin;26 mm²
Outline Drawing: 21-0140 (PDF)
Land Pattern: 90-0013 (PDF)
Use pkgcode/variation: T3255+5*
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