The MAX4885E integrates high-bandwidth analog switches and level-translating buffers to implement a complete 1:2 multiplexer for VGA signals. The device provides switching for RGB, display data channel (DDC).
Horizontal and vertical synchronization (HSYNC/VSYNC) inputs feature level-shifting buffers to support low-voltage CMOS or standard TTL-compatible graphics controllers, meeting the VESA requirement of ±8mA. DDC, consisting of SDA_ and SCL_, is a bidirectional active-level translating switch that reduces capacitive load. The MAX4885E features high ESD protection to ±15kV Human Body Model (HBM) on all twelve externally routed terminals. See the Pin Description section in the full data sheet. All other pins are protected to ±10kV Human Body Model (HBM).
The MAX4885E is specified over the extended -40°C to +85°C temperature range, and is available in the 24-pin, 4mm x 4mm TQFN package.
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
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MAX4885E
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TYPE PINS FOOTPRINT
DRAWING CODE/VAR *
Temp
RoHS/Lead-Free? Materials Analysis
MAX4885EETG+
Active
TQFN;24 pin;16.8 mm²
Outline Drawing: 21-0139 (PDF)
Land Pattern: 90-0022 (PDF)
Use pkgcode/variation: T2444+4*
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