The MAX3674 is a high-performance network clock synthesizer IC for networking, computing, and telecom applications. It integrates a crystal oscillator, a low-noise phase-locked loop (PLL), programmable dividers, and high-frequency LVPECL output buffers. The PLL generates a high-frequency clock based on a low-frequency reference clock provided by the on-chip crystal oscillator or an external LVCMOS clock. The MAX3674 has excellent period jitter, cycle-to-cycle jitter, and supply noise rejection performance. With output frequencies programmable from 21.25MHz to 1360MHz and support of two differential PECL output signals, the device provides a versatile solution for the most demanding clock applications.
Programming is accomplished through a 2-wire I²C bus or parallel interface that can change the output frequency on demand for frequency margining. Both LVPECL outputs have synchronous stop functionality, and the PLL has a LOCK indicator output. The MAX3674 operates from a +3.3V supply and typically consumes 396mW. The device is packaged in a 48-pin LQFP, and the operating temperature range is from -40°C to +85°C.
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
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MAX3674
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TYPE PINS FOOTPRINT
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MAX3674ECM+
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TQFP;48 pin;85 mm²
Outline Drawing: 21-0054 (PDF)
Land Pattern: 90-0093 (PDF)
Use pkgcode/variation: C48+3*
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