The MAX3674 is a high-performance network clock synthesizer IC for networking, computing, and telecom applications. It integrates a crystal oscillator, a low-noise phase-locked loop (PLL), programmable dividers, and high-frequency LVPECL output buffers. The PLL generates a high-frequency clock based on a low-frequency reference clock provided by the on-chip crystal oscillator or an external LVCMOS clock. The MAX3674 has excellent period jitter, cycle-to-cycle jitter, and supply noise rejection performance. With output frequencies programmable from 21.25MHz to 1360MHz and support of two differential PECL output signals, the device provides a versatile solution for the most demanding clock applications.
Programming is accomplished through a 2-wire I²C bus or parallel interface that can change the output frequency on demand for frequency margining. Both LVPECL outputs have synchronous stop functionality, and the PLL has a LOCK indicator output. The MAX3674 operates from a +3.3V supply and typically consumes 396mW. The device is packaged in a 48-pin LQFP, and the operating temperature range is from -40°C to +85°C.
Key Features
Applications/Uses
21.25MHz to 1360MHz Programmable PLL Synthesized Output Clocks
Two Differential LVPECL-Compatible Outputs
Cycle-to-Cycle Jitter 1.6ps RMS and Period Jitter 0.9ps RMS at 500MHz
On-Chip Crystal Oscillator or Selectable LVCMOS-Compatible Reference Clock Input
Excellent Power-Supply Noise Rejection
Parallel or 2-Wire I²C Programming Interface
Lock Indicator Output
+3.3V Power Supply
Power Consumption: 396mW at 3.3V
48-Pin LQFP Pb-Free Package
-40°C to +85°C Temperature Range
Ethernet Network ASIC Clock Generation
Frequency Margining
Optical Network ASIC Clocking
Programmable Clock Source for Server, Computing, or Communication Systems
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