The MAX3624 is a low-jitter precision clock generator
optimized for networking applications. The device integrates
a crystal oscillator and a phase-locked loop
(PLL) clock multiplier to generate high-frequency clock
outputs for Ethernet, Fibre Channel, SONET/SDH, and
other networking applications.
Maxim's proprietary PLL design features ultra-low jitter
(0.36psRMS) and excellent power-supply noise rejection,
minimizing design risk for network equipment.
The MAX3624 has three LVPECL outputs and one
LVCMOS output. Selectable output dividers and a
selectable feedback divider allow a range of output
frequencies.
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
Devices:
1-2 of 2
MAX3624
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Status
Package:
TYPE PINS FOOTPRINT
DRAWING CODE/VAR *
Temp
RoHS/Lead-Free? Materials Analysis
MAX3624UTJ+
Active
TQFN;32 pin;26 mm²
Outline Drawing: 21-0140 (PDF)
Land Pattern: 90-0001 (PDF)
Use pkgcode/variation: T3255+3*
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