- Advanced DPLL Technology
- Programmable PLL Bandwidth: 18Hz to 400Hz
- Manual Reference Switching
- Holdover on Loss of All Input References
- Frequency Conversion Among SONET/SDH, PDH, Ethernet, Wireless, and CMTS Rates
- Two Input Clocks
- CMOS/TTL Signal Format (≤ 125MHz)
- Numerous Input Clock Frequencies Supported
- Ethernet xMII: 2.5, 25, 125, 156.25MHz
- SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
- PDH: N x DS1, N x E1, N x DS2, DS3, E3
- Frame Sync: 2kHz, 4kHz, 8kHz
- Custom Clock Rates: Any Multiple of 2kHz Up to 125MHz
- Two Output Clocks
- One CMOS/TTL Output (≤ 125MHz)
- One LVDS/LVPECL Output (≤ 312.50MHz)
- Two Optional Frame-Sync Outputs: 2kHz, 8kHz
- Numerous Output Clock Frequencies Supported
- Ethernet xMII: 2.5, 25, 125, 156.25, 312.5MHz
- SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
- PDH: N x DS1, N x E1, N x DS2, DS3, E3
- Other: 10, 10.24, 13, 30.72MHz
- Frame Sync: 2kHz, 8kHz
- Custom Clock Rates: Any Multiple of 2kHz Up to 77.76MHz, Any Multiple of 8kHz Up to 311.04MHz, Any Multiple of 10kHz Up to 388.79MHz
- General
- Suitable Line Card IC for Stratum 3/3E/4, SMC, SEC
- Internal Compensation for Master Clock Oscillator
- SPI™ Processor Interface
- 1.8V Operation with 3.3V I/O (5V Tolerant)
- Industrial Operating Temperature Range
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| SONET/SDH, Synchronous Ethernet, PDH, and Other Line Cards in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Wireless Base Stations
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