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MAX9396
2:1 Multiplexer and 1:2 Demultiplexer with Loopback

Multiplexer/Demultiplexer with 450mV Differential Output


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Status
Active: In Production.

Data Sheet
FULL DATA SHEET (PDF, 168kB)
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Description
The MAX9396 consists of a 2:1 multiplexer and a 1:2 demultiplexer with loopback. The multiplexer section (channel B) accepts two differential inputs and generates a single differential output. The demultiplexer section (channel A) accepts a single differential input and generates two parallel differential outputs. The MAX9396 features a loopback mode that connects the input of channel A to the output of channel B and connects the selected input of channel B to the outputs of channel A.

The differential inputs of the MAX9396 accept CML/LVPECL levels and can also accept LVDS inputs with common-mode voltages from +0.6V to (VCC - 0.05V). The differential outputs are LVDS compatible and drive 100Ω loads.

Three LVCMOS/LVTTL logic inputs control the internal connections between inputs and outputs, one for the multiplexer portion of channel B (BSEL), and the other two for loopback control of channels A and B (LB_SELA and LB_SELB). Independent enable inputs for each differential output pair provide additional flexibility.

Fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the commonmode voltage is below +0.6V.

Ultra-low 57psP-P (typ) pseudorandom bit sequence (PRBS) jitter ensures reliable communications in high-speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. The high-speed switching performance guarantees 1.25Gbps operation and less than 87ps (max) skew between channels.

The MAX9396 is available in a 32-pin TQFP package and is specified over the -40°C to +85°C extended temperature range.

Key Features   Applications/Uses
  • Guaranteed 1.25Gbps Operation with 450mV (min) Differential Output Swing
  • Integrated 100Ω Resistors on Differential Inputs
  • Simultaneous Loopback Control
  • 2ps(RMS) (max) Random Jitter
  • AC Specifications Guaranteed for 150mV Differential Input
  • Signal Inputs Accept Any Differential Signals with VCM = +0.6V to (VCC - 0.05V)
  • LVDS Outputs for Clock or High-Speed Data
  • Low-Level Input Fail-Safe Detection
  • +3.0V to +3.6V Supply Voltage Range
  • LVCMOS/LVTTL Logic Inputs

 
  • Central Office Backplane Clock Distribution
  • DSLAM
  • Fault-Tolerant Systems
  • High-Speed Telecom/Datacom Equipment
  • Protection Switching

    Diagram
    MAX9396: Typical Operating Circuit
    Typical Operating Circuit

    Design Guides
  • Wireless Infrastructure (PDF)
  • High-Speed Interconnect (PDF)

    Reliability Reports
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    Software/Models
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    Ordering Information
    Notes:

    1. Other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales.
    2. Didn't Find What You Need? Ask our applications engineers. Expert assistance in finding parts, usually within one business day.
    3. Part number suffixes: T or T&R = tape and reel;+ = RoHS/lead-free;# = RoHS/lead-exempt. More: SeeFull Data Sheet or Part Naming Conventions.
    4. * Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.


    Devices: 1-2 of 2

    MAX9396 Free
    Sample
    Buy Status
    Package: TYPE PINS FOOTPRINT
      DRAWING CODE/VAR *
    Temp RoHS/Lead-Free?
    Materials Analysis
    MAX9396EHJ+  
    Active TQFP;32 pin;51.8 mm²
    Outline Drawing: 21-0110 (PDF)
    Land Pattern: 90-0149 (PDF)
    Use pkgcode/variation: H32+1*
    -40°C to +85°C RoHS/Lead-Free: Lead Free
    Materials Analysis
    MAX9396EHJ+T    
    Active TQFP;32 pin;51.8 mm²
    Outline Drawing: 21-0110 (PDF)
    Land Pattern: 90-0149 (PDF)
    Use pkgcode/variation: H32+1*
    -40°C to +85°C RoHS/Lead-Free: Lead Free
    Materials Analysis

    Related Products
    MAX9394, MAX9395 2:1 Multiplexers and 1:2 Demultiplexers with Loopback

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    Document Ref.: 19-0736; Rev 0; 2007-01-31
    This page last modified: 2007-02-06


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