The MAX9396 consists of a 2:1 multiplexer and a 1:2
demultiplexer with loopback. The multiplexer section
(channel B) accepts two differential inputs and generates
a single differential output. The demultiplexer section
(channel A) accepts a single differential input and
generates two parallel differential outputs. The
MAX9396 features a loopback mode that connects the
input of channel A to the output of channel B and connects
the selected input of channel B to the outputs of
channel A.
The differential inputs of the MAX9396 accept
CML/LVPECL levels and can also accept LVDS inputs
with common-mode voltages from +0.6V to (VCC -
0.05V). The differential outputs are LVDS compatible
and drive 100 loads.
Three LVCMOS/LVTTL logic inputs control the internal
connections between inputs and outputs, one for the
multiplexer portion of channel B (BSEL), and the other
two for loopback control of channels A and B (LB_SELA
and LB_SELB). Independent enable inputs for each differential
output pair provide additional flexibility.
Fail-safe circuitry forces the outputs to a differential low
condition for undriven inputs or when the commonmode
voltage is below +0.6V.
Ultra-low 57psP-P (typ) pseudorandom bit sequence
(PRBS) jitter ensures reliable communications in high-speed
links that are highly sensitive to timing error,
especially those incorporating clock-and-data recovery,
or serializers and deserializers. The high-speed switching
performance guarantees 1.25Gbps operation and
less than 87ps (max) skew between channels.
The MAX9396 is available in a 32-pin TQFP package
and is specified over the -40°C to +85°C extended temperature
range.
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