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DS34T101, DS34T102, DS34T104, DS34T108
Single/Dual/Quad/Octal TDM-Over-Packet Chip

Supports CESoPSN, SAToP, and TDMoIP Transport Over a Packet-Switched Network for Up to 8 E1/T1 Ports


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Status
Active: In Production.

Description
ABRIDGED DATA SHEET (PDF, 272kB)
Download this datasheet in PDF formatDownload Request Full Data Sheet
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. TDM data is transported in up to 64 individually configurable bundles. All standards-based TDM-over-packet mapping methods are supported except AAL2. Frame-based serial HDLC data flows are also supported. With built-in full-featured E1/T1 framers and LIUs. These ICs encapsulate the TDM-over-packet solution from analog E1/T1 signal to Ethernet MII while preserving options to make use of TDM streams at key intermediate points. The high level of integration available with the DS34T10x devices minimizes cost, board space, and time to market.

An evaluation kit is available:  DS34T108DK  

Key Features   Applications/Uses
  • Full-Featured IC Includes E1/T1 LIUs and Framers, TDMoP Engine, and 10/100 MAC
  • Transport of E1, T1, E3, T3 or STS-1 TDM or CBR Serial Signals Over Packet Networks
  • Full Support for These Mapping Methods: SAToP, CESoPSN, TDMoIP (AAL1), HDLC, Unstructured, Structured, Structured with CAS
  • Adaptive Clock Recovery, Common Clock, External Clock and Loopback Timing Modes
  • On-Chip TDM Clock Recovery Machines, One Per Port, Independently Configurable
  • Clock Recovery Algorithm Handles Network PDV, Packet Loss, Constant Delay Changes, Frequency Changes and Other Impairments
  • 64 Independent Bundles/Connections
  • Multiprotocol Encapsulation Supports IPv4, IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet
  • VLAN Support According to 802.1p and 802.1Q
  • 10/100 Ethernet MAC Supports MII/RMII/SSMII
  • Selectable 32-Bit, 16-Bit or SPI Processor Bus
  • Operates from Only Two Clock Signals, One for Clock Recovery and One for Packet Processing
  • Glueless SDRAM Buffer Management
  • Low-Power 1.8V Core, 3.3V I/O

 
  • TDM Circuit Extension Over PSN
  • Leased-Line Services Over PSN
  • TDM Over G/E-PON
  • TDM Over Cable
  • TDM Over WiMAX
  • Cellular Backhaul Over PSN
  • Multiservice Over Unified PSN
  • HDLC-Based Traffic Transport Over PSN

    Key Specifications:  TDM-Over-Packet
    Part Number Integrated T1/E1 LIU+Framer T1/E1/Serial Streams T3/E3, STS-1 Serial Ports Mapping Methods PSN Encapsulation Protocols 10/100 MAC Interface Processor Interface Package/Pins Smallest Available Pckg.
    (mm2)
    Price
    max w/pins See Notes
    DS34T101  1 1 1
    AAL1
    CESoPSN
    HDLC
    SAToP
    Structured
    Structured with CAS
    TDMoIP
    Unstructured
    L2TPv3 (IPv4, IPv6)
    MEF-8
    MPLS
    RTP
    UDP (IPv4, IPv6)
    MII
    RMII
    SSMII
    16-Bit
    32-Bit
    SPI
    BGA/484
    529 $35.31 @1k
    DS34T102  2 2
    BGA/484
    $43.03 @1k
    DS34T104  4 4
    BGA/484
    $52.97 @1k
    DS34T108  8 8
    BGA/484
    $79.45 @1k
    See All TDM-Over-Packet (9)

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    Document Ref.: 19-4835; 2009-08-21
    This page last modified: 2009-08-21


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