The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be transported transparently through a switched IP or MPLS packet network. Jitter and wander of
recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. This eliminates the need for remote timing sources in cabinets and pedestals.
The Ethernet side of the DS34T108 provides high QoS capabilities to its MII/RMII/SSMII port, while the WAN side supports full-featured T1/E1 framers and
LIUs. This takes the solution all the way through analog, while preserving options to make use of TDM streams at key intermediate points. The high level of
integration that the DS34T108 brings minimizes cost, board space, and time to market.
Key Features
Applications/Uses
Full-Featured T1/E1/J1 LIU/Framer/TDM-Over-Packet
Supports Adaptive Clock Recovery, Common Clock (Using RTP), External Clock, and Loopback Timing Modes
Selectable 32-Bit or 16-Bit Processor Bus
Clock Rate Adapter for T1/E1 Master Clock
10/100 Ethernet MAC That Supports MII/RMII/SSMII
Fully Compatible with IEEE 802.3 Standard
VLAN Support According to 802.1 p&Q
Multiprotocol Encapsulation Supports IPv4, IPv6, UDP, RTP, L2TPv3, MPLS, and Metro Ethernet
End-to-End TDM Synchronization Through the IP/MPLS Domain by Eight Independent On-Chip TDM Clock Recovery Mechanisms
Single Serial Support for RS-530 and V.35
Single DS3/E3/STS-1 to Ethernet
Packet Loss Compensation and Handling of Misordered Packets
64 Independent Bundle/Connections
Glueless SDRAM Buffer Management
1.8V Core, 3.3V I/O
Complies with IETF PWE3 RFCs and Drafts for CESoPSN, SAToP, TDMoIP, and HDLC
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