When paired with an external TCXO or OCXO, the DS3101 is a highly integrated central timing and synchronization solution for SONET/SDH network elements. With 14 input clocks, the device directly accepts both line timing from a large number of line cards and external timing from external DS1/E1 BITS transceivers. All input clocks are continuously monitored for frequency accuracy and activity. Any two of the input clocks can be selected as the references for the two core DPLLs. The T0 DPLL complies with the Stratum 2, 3E, 3, 4E and 4 requirements of GR1244, GR-253, G.812 Types I–IV, G.813 and G.8262. From the output of the core DPLLs, a wide variety of output clock frequencies and frame pulses can be produced simultaneously on the 11 output clock pins. Two DS3101 devices can be configured in a master/slave arrangement for timing card equipment protection.
The DS3101 registers and I/O pins are backward compatible with Semtech's ACS8520 and ACS8530 timing card ICs. The DS3101 is functionally equivalent to a DS3100 without integrated BITS transceivers.
Key Features
Applications/Uses
Synchronization Subsystem for Stratum 2, 3E, 3, 4E and 4 plus SMC, SEC and EEC
Meets Requirements of GR-1244 Stratum 2–4, GR-253, G.812 Types I–IV, G.813 and G.8262
Stratum 2, 3E or 3 Holdover Accuracy with Suitable External Oscillator
Programmable Bandwidth, 0.5mHz to 70Hz
Hitless Reference Switching on Loss of Input
Phase Build-Out and Transient Absorption
Locks To and Generates 125MHz for Gigabit Synchronous Ethernet per ITU-T G.8261
14 Input Clocks
10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any Multiple of 8kHz Up to 125MHz
Two LVDS/LVPECL/CMOS/TTL Inputs Accept Nx8kHz Up to 125MHz Plus 155.52MHz
Two 64kHz Composite Clock Receivers
Continuous Input Clock Quality Monitoring
Separate 2/4/8kHz Frame Sync Input
11 Output Clocks
Five CMOS/TTL Outputs Drive Any Internally Produced Clock Up to 77.76MHz
Two LVDS Outputs Each Drive Any Internally Produced Clock Up to 311.04MHz
Download
E-Mail