The MAX9223/MAX9224 serializer/deserializer chipsets reduce wiring by serializing 22 bits onto a single differential pair. 22 bits are serialized in each cycle of the parallel input clock resulting in a 110Mbps to 220Mbps net serial-data rate ideal for cell phone QVGA and QCIF displays. The MAX9223 serializes the 18-bit RGB, VSYNC, HSYNC, and two control signals from the baseband processor to reduce wiring through the hinge to the LCD controller. The 2-wire serial interface uses low-current differential signaling (LCDS) for low EMI, high common-mode noise immunity, and ground-shift tolerance. The MAX9223/MAX9224 automatically identify the word boundary in serial data in case of signal interruption. The MAX9224 power-down is controlled by the MAX9223. The MAX9223 and MAX9224 consume 3.5µA or less in power-down mode.
The MAX9223 serializer operates from a single +2.375V to +3.465V supply and accepts +1.71V to +3.465V inputs. The MAX9224 deserializer operates from a +2.375V to +3.465V core supply and has a separate output buffer supply (VDDO), allowing +1.71V to +3.465V output high levels.
The MAX9223/MAX9224 are specified over the -40°C to +85°C extended temperature range and are available in 28-pin TQFN (4mm x 4mm x 0.8mm) packages with an exposed paddle.
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