The MAX3420E contains the digital logic and analog
circuitry necessary to implement a full-speed USB
peripheral compliant to USB specification rev 2.0. A
built-in full-speed transceiver features ±15kV ESD protection
and programmable USB connect and disconnect.
An internal serial-interface engine (SIE) handles
low-level USB protocol details such as error checking
and bus retries. The MAX3420E operates using a register
set accessed by an SPI™ interface that operates up
to 26MHz. Any SPI master (microprocessor, ASIC, DSP,
etc.) can add USB functionality using the simple 3- or
4-wire SPI interface.
Internal level translators allow the SPI interface to run at
a system voltage between 1.71V and 3.6V. USB timed
operations are done inside the MAX3420E with interrupts
provided at completion so an SPI master does not
need timers to meet USB timing requirements. The
MAX3420E includes four general-purpose inputs and
outputs so any microprocessor that uses I/O pins to
implement the SPI interface can reclaim the I/O pins
and gain additional ones.
The MAX3420E operates over the extended -40°C to
+85°C temperature range and is available in a 32-pin
LQFP package (7mm x 7mm) and a space-saving 24-pin TQFN package (4mm x 4mm).
Key Features
Applications/Uses
Microprocessor-Independent USB Solution
Complies with USB Specification Revision 2.0 (Full-Speed Operation)
Integrated Full-Speed USB Transceiver
Firmware/Hardware Control of an Internal D+ Pullup Resistor
Programmable 3- or 4-Wire 26MHz SPI Interface
Level Translators and VL Input Allow Independent System Interface Voltage
Internal Comparator Detects VBUS for Self-Powered Applications
ESD Protection on D+, D-, and VBCOMP
Interrupt Output Pin (Level or Programmable Edge) Allows Polled or Interrupt-Driven SPI Interface
Intelligent USB Serial-Interface Engine (SIE)
Automatically Handles USB Flow Control and Double Buffering
Handles Low-Level USB Signaling Details
Contains Timers for USB Time-Sensitive Operations So SPI Master Does Not Need to Time Events
Built-In Endpoint FIFOs
EP0: CONTROL (64 Bytes)
EP1: OUT, Bulk or Interrupt, 2 x 64 Bytes (Double-Buffered)
EP2: IN, Bulk or Interrupt, 2 x 64 Bytes (Double-Buffered)
EP3: IN, Bulk or Interrupt (64 Bytes)
Double-Buffered Data Endpoints Increase Throughput by Allowing the SPI Master to Transfer Data Concurrently with USB Transfers Over the Same Endpoint
SETUP Data Has Its Own 8-Byte FIFO, Simplifying Firmware
Four General-Purpose Inputs and Four General-Purpose Outputs
Notes: **This pricing is BUDGETARY, for comparing similar parts. Prices are in
U.S. dollars and subject to change. Quantity pricing may vary
substantially and international prices may differ due to local
duties, taxes, fees, and exchange rates. For volume-specific prices
and delivery, please see the price and availability page
or contact an authorized distributor.
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