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DS33Z41 Quad IMUX Ethernet Mapper

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Status

Active: In Production.

Description

FULL DATA SHEET (PDF, 980kB)

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The DS33Z41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over up to four interleaved PDH/TDM data streams using robust, balanced, and programmable inverse multiplexing. The Interleave Bus (IBO) serial link supports seamless bidirectional interconnection with Dallas Semiconductor's T1/E1 framers and transceivers.
The device performs store-and-forward of packets with full wire-speed transport capability. The built-in Committed Information Rate (CIR) Controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps.

An evaluation kit is available: DS33Z41DK

Key Features Applications/Uses

10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control
Layer 1 Inverse Multiplexing Allows Bonding of Up to 4 T1/E1/J1 or DSL Links
Supports Up to 7.75ms Differential Delay
Channel (Byte) Interleaved Bus Operation
In-Band OAM and Signaling Capability
HDLC/LAPS Encapsulation with Programmable FCS, Interframe Fill
Committed Information Rate Controller Provides Fractional Allocation in 512kbps Increments
Programmable BERT for the Serial Interface
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
1.8V Operation with 3.3V Tolerant I/O
IEEE 1149.1 JTAG Support

Bonded Transparent LAN Service
Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4
LAN Extension