| 10/100 IEEE 802.3 Ethernet MAC (MII and
RMII) Half/Full Duplex with Automatic Flow
Control
|
| Layer 1 Inverse Multiplexing Allows Bonding of
Up to 4 T1/E1/J1 or DSL Links
|
| Supports Up to 7.75ms Differential Delay
|
| Channel (Byte) Interleaved Bus Operation
|
| In-Band OAM and Signaling Capability
|
| HDLC/LAPS Encapsulation with Programmable
FCS, Interframe Fill
|
| Committed Information Rate Controller Provides
Fractional Allocation in 512kbps Increments
|
| Programmable BERT for the Serial Interface
|
| External 16MB, 100MHz SDRAM Buffering
|
| Parallel Microprocessor Interface
|
| 1.8V Operation with 3.3V Tolerant I/O
|
| IEEE 1149.1 JTAG Support |
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