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Active: In Production.

Description

FULL DATA SHEET (PDF, 908kB) Download   E-Mail The DS3251 (single), DS3252 (dual), DS3253 (triple), and DS3254 (quad) line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit paths and a built-in jitter attenuator. An on-chip clock adapter generates all line-rate clocks from a single input clock. Control interface options include 8-bit parallel, SPI, and hardware mode.

An evaluation kit is available:  DS3254DK  

Key Features		Applications/Uses
Pin-Compatible Family of Products Each Port Independently Configurable Receive Clock and Data Recovery for up to 380 meters (DS3), 440 meters (E3), or 360 meters (STS-1) of 75Ω Coaxial Cable Standards-Compliant Transmit Waveshaping Three Control Interface Options: 8-Bit Parallel, SPI, and Hardware Mode Built-In Jitter Attenuators can be Placed in Either the Receive or Transmit Paths Jitter Attenuators Have Provisionable Buffer Depth: 16, 32, 64, or 128 Bits Built-In Clock Adapter Generates All Line-Rate Clocks from a Single Input Clock (DS3, E3, STS-1, OC-3, 19.44MHz, 38.88MHz, 77.76MHz) B3ZS/HDB3 Encoding and Decoding Minimal External Components Required Local and Remote Loopbacks Low-Power 3.3V Operation (5V Tolerant I/O) Industrial Temperature Range: -40°C to +85°C Small Package: 144-Pin, 13mm x 13mm Thermally Enhanced CSBGA Drop-In Replacement for DS3151/DS3152/DS3153/DS3154 LIUs IEEE 1149.1 JTAG Support		Access Concentrators ATM and Frame Relay Equipment CSUs/DSUs Digital Cross-Connects DSLAMs PBXs Routers/Switches SONET/SDH and PDH Multiplexers

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