The DS33R41 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over four interleaved
T1/E1/J1 lines using a robust, balanced, and
programmable inverse multiplexing. Four integrated
T1/E1/J1 transceivers provide framing and line
interfacing functionality.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
committed information rate (CIR) controller provides
fractional bandwidth allocation up to the line rate in
increments of 512kbps.
Key Features
Applications/Uses
10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control
Layer 1 Inverse Multiplexing Over Four T1/E1/J1 Lines Through the Integrated Framers and LIUs
Supports Up to 7.75ms Differential Delay
Aggregate Bandwidth from Up to Four T1/E1/J1 Links
T1/E1 Signaling Capability for OAM
HDLC/LAPS Encapsulation with Programmable FCS, Interframe Fill
CIR Controller Provides Fractional Allocations in 512kbps Increments
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
Devices:
1-2 of 2
DS33R41
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Status
Package:
TYPE PINS FOOTPRINT
DRAWING CODE/VAR *
Temp
RoHS/Lead-Free? Materials Analysis
DS33R41
Active
PBGA;400 pin;729 mm²
Outline Drawing: 21-0305 (PDF)
Land Pattern: 90-0265 (PDF)
Use pkgcode/variation: V400T-1*
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