The DS26556 is a quad, software-selectable T1, E1, or J1 transceiver with a cell/packet/TDM interface. It is composed of four framer/formatters + LIUs, and a UTOPIA (cell), POS-PHY™ (packet), and TDM backplane interface. Each
framer has an HDLC controller that can be mapped to any DS0 or FDL (T1)/Sa (E1) bit. The DS26556 also includes full-featured BERT devices per port, and an internal clock adapter useful for creating synchronous, high-frequency backplane timing. The DS26556 is controlled through an 8-bit parallel port that can be
configured for nonmultiplexed Intel or Motorola operation.
Key Features
Applications/Uses
Four Independent, Full-Featured T1/E1/J1 Transceivers
UTOPIA 2 and 3 Cell Interface
POS-PHY 2 and 3 Packet Interface
TDM Backplane Supports TDM Bus Rates from 1.544MHz to 16.384MHz
Alarm Detection and Insertion
Full-Featured BERT for Each Port
AMI, B8ZS, HDB3, NRZ Line Coding
Transmit Synchronizer
BOC Message Controller (T1)
One HDLC Controller per Framer
Performance Monitor Counters
RAI-CI and AIS-CI Support
Internal Clock Generator (CLAD) Supplies 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
Notes: **This pricing is BUDGETARY, for comparing similar parts. Prices are in
U.S. dollars and subject to change. Quantity pricing may vary
substantially and international prices may differ due to local
duties, taxes, fees, and exchange rates. For volume-specific prices
and delivery, please see the price and availability page
or contact an authorized distributor.
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
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