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MAX9489
Multiple-Output Network Clock Generator

Clock Generator Provides Multiple Clock Outputs Ideal for Network Routers


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Status
Active: In Production.

Description
FULL DATA SHEET (PDF, 192kB)
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The MAX9489 clock generator provides multiple clock outputs, ideal for network routers. The MAX9489 provides 15 buffered clock outputs, each independently programmable to any of 10 individual frequencies: 133MHz, 125MHz, 100MHz, 83MHz, 80MHz, 66MHz, 62.5MHz, 50MHz, 33MHz, or 25MHz. All of the outputs are single-ended LVCMOS. The MAX9489 is controlled through its I²C interface.

At power-up, the frequency of output CLK1 is set by the tri-level input SEL to 100MHz, 125MHz, or 133MHz, while all other outputs are logic low. All outputs are then programmable to any available frequency through the I²C interface. Additionally, all output frequencies are adjustable up or down, by a margin of 5% or 10%, through the I²C interface.

The MAX9489 requires a 25MHz reference that can be either a crystal or an external clock signal. The MAX9489 requires a +3.0V to +3.6V power supply and is available in a 32-pin thin QFN package with an exposed pad for heat removal.

Key Features   Applications/Uses
  • 15 LVCMOS Outputs with 10 Independently Programmable Frequencies: 133MHz, 125MHz, 100MHz, 83MHz, 80MHz, 66MHz, 62.5MHz, 50MHz, 33MHz, and 25MHz
  • 25MHz Crystal or Clock Input Reference
  • Programmable Through I²C Interface
  • Programmable Output Frequency Margin of ±5% or ±10%
  • Pin-Selectable Power-Up Frequency for CLK1 Output: 100MHz, 125MHz, or 133MHz
  • Low Output Period Jitter: < 48psRMS
  • Output-to-Output Skew < 200ps
  • Available in 32-Lead, 5mm x 5mm x 0.8mm, Thin QFN Package
  • Operates from +3.0V to +3.6V Power Supply
  • Power Dissipation 450mW (typ)
  • Extended Temperature Range: -40°C to +85°C
 

Key Specifications:  Clock Generators
Part Number Applications fIN
(MHz)
fIN
(MHz)
fOUT
(MHz)
fOUT
(MHz)
Fixed or Continuous Frequency Output Levels Out-
puts
PLLs Program-
mability
Spread Spectrum Output Jitter
(ps)
VSUPPLY
(V)
Package/Pins
min max min max RMS
MAX9489 
Ethernet
General Purpose
10 25 25 133.3 Fixed LVCMOS 15 2 I2C No 48 3.3
TQFN/32
See All Clock Generators (25)

Diagram
MAX9489: Typical Operating Circuit
Typical Operating Circuit

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    Document Ref.: 19-3385; Rev 0; 2004-08-25
    This page last modified: 2009-10-07


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