The MAX3610 is a low-jitter, high-performance, dual-rate
clock generator optimized for 1Gbps/2Gbps/4Gbps
Fibre-Channel applications. When connected with an
external AT-cut crystal, the device generates a precision
clock output by integrating a crystal oscillator with
Maxim's low-noise phase-locked loop (PLL) providing a
low-cost solution. By coupling Maxim's low-noise PLL
design featuring a low-jitter generation VCO with an
inexpensive fundamental mode crystal, the MAX3610
provides the optimum combination of low cost, flexibility,
and high performance.
The MAX3610 output frequency is selectable. When
using a 26.5625MHz crystal, the output clock rate can
be set to either 106.25MHz or 212.5MHz. When operating
at 106.25MHz, the typical phase jitter is 0.7psRMS
from 12kHz to 20MHz. The MAX3610A has low-voltage
positive-emitter-coupled logic (LVPECL) clock output
drivers. The MAX3610B has low-voltage differential-signal
(LVDS) clock output drivers. The MAX3610 output
drivers can also be disabled.
The MAX3610 operates from a single +3.3V supply.
The PECL version typically consumes 165mW, while the
LVDS version typically consumes 174mW. Both devices
are available in die form and have a 0°C to +85°C operating
temperature range.
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
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