The MAX5866 ultra-low-power, highly integrated analog front end is ideal for portable communication equipment such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5866 integrates dual, 8-bit receive ADCs and dual, 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs' analog I-Q input amplifiers are fully differential and accept 1VP-P full-scale signals. Typical I-Q channel phase matching is ±0.2° and amplitude matching is ±0.05dB. The ADCs feature 48dB SINAD and 70.1dBc spurious-free dynamic range (SFDR) at fIN = 25MHz and fCLK = 60MHz. The DACs' analog I-Q outputs are fully differential with ±400mV full-scale output, and 1.4V common-mode level. Typical I-Q channel phase matching is ±0.4° and gain matching is ±0.1dB. The DACs also feature dual, 10-bit resolution with 64.2dBc SFDR, at fOUT = 6MHz and fCLK = 60MHz.
The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface controls power-down and transceiver modes of operation. The typical operating power is 96mW at fCLK = 60MHz with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5866 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5866 operates on a +2.7V to +3.3V analog power supply and a +2.7V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 12mA in idle mode and 1µA in shutdown mode. The MAX5866 is specified for the extended (-40°C to +85°C) temperature range and is available in a 48-pin thin QFN package. See a parametric table of the complete family of pin-compatible AFEs.
Key Features
Applications/Uses
Integrated Dual, 8-Bit ADCs and Dual, 10-Bit DACs
Ultra-Low Power
80mW at fCLK = 60MHz (Rx Mode)
52.5mW at fCLK = 60MHz (Tx Mode)
Low-Current Idle and Shutdown Modes
Excellent Dynamic Performance
48dB SINAD at fIN = 25MHz (ADC)
64.2dBc SFDR at fOUT = 6MHz (DAC)
Excellent Gain/Phase Match
±0.2° Phase, ±0.05dB Gain at fIN = 25MHz (ADC)
Internal/External Reference Option
+2.7V to +3.3V Digital Output Level (TTL/CMOS Compatible)
Multiplexed Parallel Digital Input/Output for ADCs/DACs
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