The MAX1124 is a monolithic 10-bit, 250Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high IF frequencies up to 500MHz. The product operates with conversion rates of up to 250Msps while consuming only 477mW.
At 250Msps and an input frequency of 100MHz, the MAX1124 achieves a spurious-free dynamic range (SFDR) of 71dBc. Its excellent signal-to-noise ratio (SNR) of 57.1dB at 10MHz remains flat (within 1dB) for input tones up to 500MHz. This makes the MAX1124 ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems.
The MAX1124 requires a single 1.8V supply. The analog input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 500MHz. This helps to reduce the phase noise of the input clock source. A differential LVDS sampling clock is recommended for best performance. The converter's digital outputs are LVDS compatible, and the data format can be selected to be either two's complement or offset binary.
The MAX1124 is available in a 68-pin QFN with exposed pad (EP) and is specified over the industrial (-40°C to +85°C) temperature range.
For pin-compatible, lower speed versions of the MAX1124, refer to the MAX1122 (170Msps) and the MAX1123 (210Msps) data sheets. For a pin-compatible 8-bit version of the MAX1124, refer to the MAX1121 data sheet.
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
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MAX1124
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MAX1124EGK-D
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QFN;68 pin;100 mm²
Outline Drawing: 21-0122 (PDF)
Land Pattern: 90-0245 (PDF)
Use pkgcode/variation: G6800-4*
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