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DS26524
Quad T1/E1/J1 Transceiver

Low-Power, Low-Cost SCT Pin and Software Compatible with the Octal DS26528 and Makes Migration to Higher Ports Easy, Available in Lead-Free Packages


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Status
Active: In Production.

Data Sheet
FULL DATA SHEET (PDF, 2.4MB)
Download this datasheet in PDF formatDownload   Send this datasheet to any email addressE-Mail


Errata
  • Errata DS26524 26524A3.pdf 
  • Errata DS26524 26524A4.pdf 
  • Errata DS26524 26524A5.pdf 
  • Application Notes
  • Application Note 301: Legacy T1/E1 8MHz Backplane Operation - DS26524
  • Application Note 309: Interfacing to the Fractional T1 and E1 - DS26524
  • Application Note 351: T1/E1 and T3/E3 Transformer Selection Guide - DS26524
  • Application Note 561: Tech Brief 7: DS2152 and DS2154 8MHz System Clock Operation - DS26524
  • Application Note 3718: DS26528 and DS26524 Transmit Pulse Control - DS26524
  • Application Note 3827: Initialization and Configuration of the DS26528 Transceiver - DS26524
  • Application Note 3968: How to Use the Bit-Error-Rate Tester (BERT) on the DS2652x STCs - DS26524

    Design Guides
  • Communications (PDF)

    Reliability Reports
  • Reliability Report: DS26524.pdf

    Software/Models
  • DS26524CSBGA BSDL Model
  • DS26524 BSDL Model

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    Document Ref.: xxxx; 2007-12-05
    This page last modified: 2007-12-05


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