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MAX9394, MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with Loopback

2:1 Multiplexers and 1:2 Demultiplexers with Loopback Guaranteed to Operate at 1.35GHz fMAX


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Status
Active: In Production.

Description
FULL DATA SHEET (PDF, 184kB)
Download this datasheet in PDF formatDownload   Send this datasheet to any email addressE-Mail
The MAX9394/MAX9395 consist of a 2:1 multiplexer and a 1:2 demultiplexer with loopback. The multiplexer section (channel B) accepts two low-voltage differential signaling (LVDS) inputs and generates a single LVDS output. The demultiplexer section (channel A) accepts a single LVDS input and generates two parallel LVDS outputs. The MAX9394/MAX9395 feature a loopback mode that connects the input of channel A to the output of channel B and connects the selected input of channel B to the outputs of channel A.

Three LVCMOS/LVTTL logic inputs control the internal connections between inputs and outputs, one for the multiplexer portion of channel B (BSEL), and the other two for loopback control of channels A and B (LB_SELAand LB_SELB). Independent enable inputs for each differential output pair provide additional flexibility.

Fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the common-mode voltage exceeds the specified range. The MAX9394 provides high-level input fail-safe detection for HSTL, LVDS, and other GND-referenced differential inputs. The MAX9395 provides low-level fail-safe detection for CML, LVPECL, and other VCC-referenced differential inputs.

Ultra low 91psP-P (max) pseudorandom bit sequence (PRBS) jitter ensures reliable communications in high-speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. The high-speed switching performance guarantees 1.5GHz operation and less than 87ps (max) skew between channels.

LVDS inputs and outputs are compatible with the TIA/EIA-644 LVDS standard. The LVDS outputs drive 100Ω loads. The MAX9394/MAX9395 are offered in a 32-pin TQFP package and operate over the extended temperature range (-40°C to +85°C).

Key Features   Applications/Uses
  • Guaranteed 1.5GHz Operation with 250mV Differential Output Swing
  • Simultaneous Loopback Control
  • 2ps(RMS) (max) Random Jitter
  • AC Specifications Guaranteed for 150mV Differential Input
  • Signal Inputs Accept Any Differential Signaling Standard
  • LVDS Outputs for Clock or High-Speed Data
  • High-Level Input Fail-Safe Detection (MAX9394)
  • Low-Level Input Fail-Safe Detection (MAX9395)
  • 3.0V to 3.6V Supply Voltage Range
  • LVCMOS/LVTTL Logic Inputs
 
  • Central Office Backplane Clock Distribution
  • DSLAM
  • Fault-Tolerant Systems
  • High-Speed Telecom/Datacom Equipment
  • Protection Switching

Key Specifications:  High-Speed Interconnect (Differential Signaling)
Part Number Features Signal Type Signal Type Functions Rx Tx Data Rates
(Mbps)
tPD
(ps)
VSUPPLY
(V)
Price
Rx Tx max See Notes
MAX9394 
Fail-Safe Inputs
Integrated Splitter/Multiplexer
LVDS LVDS
Demultiplexer
Multiplexer
3 3 3000 720 3.3 -
MAX9395  -
See All High-Speed Interconnect (Differential Signaling) (130)

Diagram
MAX9394, MAX9395: Typical Operating Circuit
Typical Operating Circuit

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    Document Ref.: 19-2878; Rev 1; 2007-06-05
    This page last modified: 2009-10-08


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