QuickView

Technical Documents

Ordering Info

More Information

User Comments (0)

All

Status

Active: In Production.

Description

ABRIDGED DATA SHEET (PDF, 60kB) Download Request Full Data Sheet The DS5250 is a highly secure, four clocks-per-machine cycle, 100% 8051-instruction-set-compatible microprocessor in Maxim's secure microcontroller family. It was designed to be the cryptographic engine of PIN pads, financial terminals, and any other application in which data security is paramount. A key feature of the device is that it encrypts its program memory and optionally its data memory with a hardware-based single-or triple-DES (data encryption standard) algorithm, making it almost impossible to extract information. It also implements block cipher encoding that uses block addresses to modify the encrypted data, further strengthening security. This makes the device ideal for storage and transmission of passwords, personal identification numbers, encryption keys, and other highly confidential information. Note: Designers must have the following documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user's guides offer detailed information about device features and operation. DS5250 IC data sheet DS5250 revision-specific errata sheet (Click here for availability) High-Speed Microcontroller User's Guide High-Speed Microcontroller User's Guide: DS5250 Supplement

An evaluation kit is available:  DS5250-KIT  

Key Features		Applications/Uses
Feature-Rich, 8051-Compatible Microprocessor Accesses Up to 4MB Program and 4MB Data Memory (All Nonvolatile) In-System Programmable Through Serial Port In-Application Programmable Through User Software Allows Self-Modification of Program/Data Memory Four 8-Bit Ports/One 6-Bit Port Three 16-Bit Timer/Counters 256 Bytes of Scratchpad RAM Advanced Features CRC-16/32 Generator 5KB Internal SRAM (Optional 1KB Stack) Single or 3DES Engine Partitionable Memory Segments Variable from 4KB to 256KB High-Speed Architecture Four Clocks-per-Machine Cycle DC-to-25MHz Operation Single-Cycle Instruction in 160ns Dual Data Pointers Can Increment or Decrement Independently Automatic Data Pointer (DPTR) Selection Available Programmable Speed MOVX Instructions 1KB On-Chip Instruction Cache High-Reliability Operation Power-Fail/Overvoltage Reset Early-Warning Power-Fail Interrupt Watchdog Timer Nonvolatile Functions On-Chip Real-Time Clock with Alarm Interrupt 2KB Battery-Backed Internal SRAM Interrupts 15 Interrupts with Seven External Sources Security Features Executes Single/3DES-Encrypted Programs to Prevent Observation Two Self-Destruct Inputs 4096-Bit Modulo-Arithmetic Accelerator (MAA) for Public/Private Key Operations Tamper Sensors Detect Thermal/Voltage/Probe Attacks Programmable Attack Countermeasures Secure-Loader Mode True Random-Number Generator (RNG) Unique ID Number in Every Device Separate Program/Data Cryptograph Program Memory Integrity Checking Evaluation Kit Available (DS5250-KIT) Underwriters Laboratories (UL®) Recognized		Applications that Require Data Security Financial Terminals PIN Pads