- Four Complete E1, T1, or J1 LIUs
- Supports Long- and Short-Haul Trunks
- Internal Software-Selectable Receive-Side Termination for 75Ω/100Ω/120Ω
- 3.3V Power Supply
- 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Requires Only a 2.048MHz Master Clock for E1 and T1, with the Option to Use 1.544MHz for T1
- Generates the Appropriate Line Build-Outs With and Without Return Loss for E1, and DSX-1 and CSU Line Build-Outs for T1
- AMI, HDB3, and B8ZS Encoding/Decoding
- 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz Clock Output Synthesized to Recovered Clock
- Programmable Monitor Mode for Receiver
- Loopbacks and PRBS Pattern Generation/ Detection with Output for Received Errors
- Generates/Detects In-Band Loop Codes, 1 to 16 Bits, Including CSU Loop Codes
- 8-Bit Parallel or Serial Interface with Optional Hardware Mode
- Muxed and Nonmuxed Parallel Bus Supports Intel or Motorola
- Detects/Generates Blue (AIS) Alarms
- NRZ/Bipolar Interface for Tx/Rx Data I/O
- Transmit Open-Circuit Detection
- Receive Carrier Loss (RCL) Indication (G.775)
- High-Z State for TTIP and TRING
- 50mARMSTransmit Current Limiter
- JTAG Boundary Scan Test Port per IEEE 1149.1
- Meets Latest E1 and T1 Specifications Including ANSI.403-1999, ANSI T1.408, AT&T TR 62411, ITU G.703, G.704, G.706, G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703, JTI.431, TBR12, TBR13, and CTR4
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