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DS26102
16-Port Transmission Convergence Device


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Status
Part Number Status
DS26102 This product is No Longer Available.

Data Sheet
FULL DATA SHEET (PDF, 632kB)
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Description
On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering (up to 4 cells), HEC generation and insertion, cell scrambling, and converts the data to a serial stream appropriate for interfacing to a T1/E1 framer or transceiver. On the receive side, the DS26102 receives a TDM stream from a T1/E1 framer or transceiver; searches for the cell alignment; verifies the HEC; provides cell filtering, descrambling, and cell buffering; and passes the cells to an ATM device through the UTOPIA II interface. Other low-level traffic management functions are selectable for the transmit and receive paths. The DS26102 can also be used in fractional T1/E1 applications.

The DS26102 maps ATM cells to T1/E1 TDM frames as per the ATM Forum Specifications af-phy-0016.000 and af-phy-0064.000. In the receive direction, the cell delineation mechanism used for finding ATM cell boundary within T1/E1 frame is performed as per ITU I.432. The DS26102 provides a mapping solution for up to 16 T1/E1 TDM ports. The terms physical layer (PHY) and line side are used synonymously in this document and refer to the device interfacing with the line side of the DS26102. The terms ATM layer and system side are used synonymously and refer to the DS26102's UTOPIA II interface.

Key Features   Applications/Uses
  • Supports 16 T1/E1 TDM Ports
  • Supports Fractional T1/E1
  • Compliant to ATM Forum Specifications for ATM Over T1 and E1
  • Standard UTOPIA II Interface to the ATM Layer
  • Configurable UTOPIA Address Range
  • Configurable Tx FIFO Depth to 2, 3, or 4 Cells
  • Optional Payload Scrambling in Transmit Direction and Descrambling in Receive Direction per ITU I.432
  • Optional HEC Insertion in Transmit Direction with Programmable COSET Polynomial Addition
  • HEC-Based Cell Delineation
  • Single-Bit HEC Error Correction in the Receive Direction
  • Receive HEC-Errored Cell Filtering
  • Receive Idle/Unassigned Cell Filtering
  • User-Definable Cell Filtering
  • 8-Bit Mux/Nonmux, Motorola/Intel Microprocessor Interface
  • Internal Clock Generator Eliminates External High-Speed Clocks
  • Internal One-Second Timer
  • Detects/Reports Up to Eight External Status Signals with Interrupt Support
  • IEEE 1149.1 JTAG Boundary Scan Support
  • 17mm x 17mm, 256-Pin CSBGA

 
  • ATM Over T1/E1
  • DSLAMs
  • IMA
  • Routers/Switches

    Design Guides
  • Communications (PDF)

    Reliability Reports
  • Reliability Report: DS26102.pdf

    Software/Models
  • DS26102 IBIS Model
  • DS26102 BSDL Model

    Ordering Information
    Notes:

    1. Other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales.
    2. Didn't Find What You Need? Ask our applications engineers. Expert assistance in finding parts, usually within one business day.
    3. Part number suffixes: T or T&R = tape and reel;+ = RoHS/lead-free;# = RoHS/lead-exempt. More: SeeFull Data Sheet or Part Naming Conventions.
    4. * Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.


    Devices: 1-2 of 2

    DS26102 Free
    Sample
    Buy Status
    Package: TYPE PINS FOOTPRINT
      DRAWING CODE/VAR *
    Temp RoHS/Lead-Free?
    Materials Analysis
    DS26102     N/A No Longer Available

    Land Pattern: Not Available

    0°C to +70°C See data sheet
    DS26102N     N/A No Longer Available

    Land Pattern: Not Available

    -40°C to +85°C See data sheet

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    2005-03-28
    This page last modified: 2008-03-11


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