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MAX9389
Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers

Industry's First 2.5GHz LVECL/LVPECL 8:1 Multiplexer


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Status
Active: In Production.

Description
FULL DATA SHEET (PDF, 352kB)
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The MAX9389 is a fully differential, high-speed, low-jitter, 8-to-1 ECL/PECL multiplexer (mux) with dual output buffers. The device is designed for clock and data distribution applications, and features extremely low propagation delay (310ps typ) and output-to-output skew (30ps max).

Three single-ended select inputs, SEL0, SEL1, and SEL2, control the mux function. The mux select inputs are compatible with ECL/PECL logic, and are internally referenced to the on-chip reference output (VBB1, VBB2), nominally VCC - 1.425V. The select inputs accept signals between VCC and VEE. Internal pulldowns to VEE ensure a low default condition if the select inputs are left open.

The differential inputs D_, D_ -bar can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output (VBB1, VBB2). All the differential inputs have internal bias and clamping circuits that ensure a low output state when the inputs are left open.

The MAX9389 operates with a wide 2.375V to 5.5V supply range. The device is offered in 32-pin TQFP and thin QFN packages, and operates over the -40°C to +85°C extended temperature range.

Key Features   Applications/Uses
  • 310ps Propagation Delay
  • Guaranteed 2.7GHz Operating Frequency
  • 0.3psRMS Random Jitter
  • <30ps Output-to-Output Skew
  • -2.375V to -5.5V Supplies for Differential LVECL/ECL
  • +2.375V to +5.5V Supplies for Differential LVPECL/PECL
  • Outputs Low for Open Inputs
  • Dual Output Buffers
  • >2kV ESD Protection (Human Body Model)

 
  • Central Office Backplane Clock Distribution
  • DSLAM/DLC
  • High-Speed Telecom and Datacom Applications

    Key Specifications:  High-Speed Interconnect (Differential Signaling)
    Part Number Features Signal Type Signal Type Functions Rx Tx tPD
    (ps)
    VSUPPLY
    (V)
    Rx Tx max
    MAX9389  Fail-Safe Inputs
    ECL
    LVECL
    LVPECL
    PECL
    ECL
    LVECL
    LVPECL
    PECL
    Multiplexer 8 2 450
    3.3
    5
    See All High-Speed Interconnect (Differential Signaling) (132)

    Diagram
    MAX9389: Functional Diagram
    Functional Diagram

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    Document Ref.: 19-2688; Rev 0; 2003-02-05
    This page last modified: 2009-10-13


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