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MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/HSTL Clock and Data Driver

1:5 Differential (LV)PECL/(LV)ECL/HSTL Clock and Data Driver Designed for Clock and Data Distribution


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Status
Active: In Production.

Description
FULL DATA SHEET (PDF, 192kB)
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The MAX9316A is a low-skew, 1-to-5 differential driver designed for clock and data distribution. This device allows selection between two inputs: one differential and one single ended. The selected input is reproduced at five differential outputs. The differential input can be adapted to accept a single-ended input by connecting the on-chip VBB supply to one input as a reference voltage.

The MAX9316A features low output-to-output skew (20ps), making it ideal for clock and data distribution across a backplane or board. For interfacing to differential HSTL and (LV)PECL signals, this device operates over a 3.0V to 5.5V supply range, allowing high-performance clock or data distribution in systems with a nominal 3.3V or 5.0V supply. For differential (LV)ECL operation, this device operates with a -3.0V to -5.5V supply.

The MAX9316A is offered in a 20-pin wide SO package.

Key Features   Applications/Uses
  • Guaranteed 400mV Differential Output at 1.5GHz
  • Selectable Single-Ended or Differential Input
  • 130ps (max) Part-to-Part Skew at +25°C
  • 20ps Output-to-Output Skew
  • 365ps Propagation Delay
  • Synchronous Output Enable/Disable
  • On-Chip Reference for Single-Ended Inputs
  • Input Biased to Low when Open
  • Pin Compatible with MC100EL14

 
  • Automated Test Equipment (ATE)
  • Central Office Backplane Clock Distribution
  • Data and Clock Driver and Buffer
  • DSLAM Backplane
  • Low-Jitter Data Repeater
  • Precision Clock Distribution
  • Wireless Base Stations

    Key Specifications:  High-Speed Interconnect (Differential Signaling)
    Part Number Features Signal Type Signal Type Functions Rx Tx tPD
    (ps)
    VSUPPLY
    (V)
    Rx Tx max
    MAX9316A 
    Fail-Safe Inputs
    Selectable Single Ended or Differential Input
    Synchronous Output Enable
    ECL
    HSTL
    LVECL
    LVPECL
    PECL
    ECL
    LVECL
    LVPECL
    PECL
    Fan-Out Buffer 2 5 520
    3.3
    5
    See All High-Speed Interconnect (Differential Signaling) (132)

    Diagram
    MAX9316A: Typical Application Circuit
    Typical Application Circuit

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    Document Ref.: 19-2648; Rev 0; 2002-11-22
    This page last modified: 2009-10-13


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