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MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/HSTL Clock and Data Driver

1:5 Differential (LV)PECL/(LV)ECL/HSTL Clock and Data Driver Designed for Clock and Data Distribution


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Data Sheet
FULL DATA SHEET (PDF, 192kB)
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Description
The MAX9316A is a low-skew, 1-to-5 differential driver designed for clock and data distribution. This device allows selection between two inputs: one differential and one single ended. The selected input is reproduced at five differential outputs. The differential input can be adapted to accept a single-ended input by connecting the on-chip VBB supply to one input as a reference voltage.

The MAX9316A features low output-to-output skew (20ps), making it ideal for clock and data distribution across a backplane or board. For interfacing to differential HSTL and (LV)PECL signals, this device operates over a 3.0V to 5.5V supply range, allowing high-performance clock or data distribution in systems with a nominal 3.3V or 5.0V supply. For differential (LV)ECL operation, this device operates with a -3.0V to -5.5V supply.

The MAX9316A is offered in a 20-pin wide SO package.

Key Features   Applications/Uses
  • Guaranteed 400mV Differential Output at 1.5GHz
  • Selectable Single-Ended or Differential Input
  • 130ps (max) Part-to-Part Skew at +25°C
  • 20ps Output-to-Output Skew
  • 365ps Propagation Delay
  • Synchronous Output Enable/Disable
  • On-Chip Reference for Single-Ended Inputs
  • Input Biased to Low when Open
  • Pin Compatible with MC100EL14

 
  • Automated Test Equipment (ATE)
  • Central Office Backplane Clock Distribution
  • Data and Clock Driver and Buffer
  • DSLAM Backplane
  • Low-Jitter Data Repeater
  • Precision Clock Distribution
  • Wireless Base Stations

    Key Specifications:   High-Speed Interconnect (Differential Signaling)
    Part Number Features Rx Signal Type Tx Signal Type Functions Number of Rx Number of Tx Propagation Delay (max) (ps) Supply Voltage (V)
    MAX9316A 
    Fail-Safe Inputs
    Selectable Single Ended or Differential Input
    Synchronous Output Enable
    ECL
    HSTL
    LVECL
    LVPECL
    PECL
    ECL
    LVECL
    LVPECL
    PECL
    Fan-Out Buffer
    2 5 520 3.3
    5
    See All High-Speed Interconnect (Differential Signaling) (132)

    Evaluation Kits
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    Design Guides
  • Interface (PDF)
  • Fiber (PDF)

    Reliability Reports
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    Software/Models
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    Ordering Information
    Notes:

    1. Other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales.
    2. Didn't Find What You Need? Ask our applications engineers. Expert assistance in finding parts, usually within one business day.
    3. Part number suffixes: T or T&R = tape and reel; + = RoHS/lead-free; # = RoHS/lead-exempt. More: SeeFull Data Sheet or Part Naming Conventions.
    4. * Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.


    Devices: 1-2 of 2

    MAX9316A Free
    Sample
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    Package: TYPE PINS FOOTPRINT
      DRAWING CODE/VAR *
    Temp RoHS/Lead-Free?
    Materials Analysis
    MAX9316AEWP  
    SOIC(W);20 pin;138 mm²
    Outline Drawing: 21-0042 (PDF)
    Land Pattern: 90-0108 (PDF)
    Use pkgcode/variation: W20-1*
    -40°C to +85°C RoHS/Lead-Free: No
    Materials Analysis
    MAX9316AEWP-T  


    Land Pattern: Not Available

    -40°C to +85°C See data sheet

    More Information
  • New Product Press Release 2002-11-11 

    Related Products
    MAX9315 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver
    MAX9316 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver
    MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver
    MAX9326 1:9 Differential LVPECL/LVECL/HSTL Clock and Data Driver
    MAX9311, MAX9313 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
    MAX9312, MAX9314 Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

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    Document Ref.: 19-2648; Rev 0; 2002-11-22
    This page last modified: 2007-08-02


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