The DS31256 is a 256-channel HDLC controller that can handle up to 60 T1 or 64 E1 data streams or two T3 data streams. Each of the 16 physical ports can handle one, two, or four T1 or E1 data streams. The DS31256 is composed of the following blocks: Layer 1, HDLC processing, FIFO, DMA, PCI bus, and local bus.
There are 16 HDLC engines (one for each port) that are each capable of operating at speeds up to 8.192Mbps in channelized mode and up to 10Mbps in unchannelized mode. The DS31256 also has three fast HDLC engines that only reside on Ports 0, 1, and 2. They are capable of operating at speeds up to 52Mbps.
Key Features
Applications/Uses
256 Independent, Bidirectional HDLC Channels
Up to 132Mbps Full-Duplex Throughput
Supports Up to 60 T1 or 64 E1 Data Streams
16 Physical Ports (16 Tx and 16 Rx) That Can Be Independently Configured for Channelized or Unchannelized Operation
Three Fast (52Mbps) Ports; Other Ports Capable of Speeds Up to 10Mbps (Unchannelized)
Channelized Ports Can Each Handle One, Two, or Four T1 or E1 Lines
Per-Channel DS0 Loopbacks in Both Directions
Over-Subscription at the Port Level
Transparent Mode Supported
On-Board Bit Error-Rate Tester (BERT) with Automatic Error Insertion Capability
BERT Function Can Be Assigned to Any HDLC Channel or Any Port
Large 16kB FIFO in Both Receive and Transmit Directions
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
Devices:
1-2
of
2
DS31256
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Package:
TYPE PINS FOOTPRINT
DRAWING CODE/VAR *
Temp
RoHS/Lead-Free? Materials Analysis
DS31256
PBGA;256 pin;729 mm²
Outline Drawing: 21-0307 (PDF)
Land Pattern: 90-0267 (PDF)
Use pkgcode/variation: V256-2*
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