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DS2156, DS2156L, DS2156LN
T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Industry's First T1/E1/J1 Transceiver for ATM Applications


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Data Sheet
FULL DATA SHEET (PDF, 1.5MB)
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Errata
  • Errata DS2156 2156A2.pdf 
  • Application Notes
  • Application Note 324: T1/E1 Network Interface Design - DS2156
  • Application Note 351: T1/E1 and T3/E3 Transformer Selection Guide - DS2156
  • Application Note 381: Interfacing the DS2155 to the MPC8260 - DS2156
  • Application Note 384: T1/E1/J1 Dual Connector Interface - DS2156
  • Application Note 389: DS2155 Internal BERT Programming - DS2156
  • Application Note 391: NRZ Applications - DS2156
  • Application Note 393: E1 Operation of Dallas Semiconductor Framers and SCTs - DS2156
  • Application Note 394: HDLC Configuration of Framers and Transceivers - DS2156
  • Application Note 405: Power-Fault Protection Layout - DS2156
  • Application Note 461: Programming and Controlling the FDL on DS2141A, DS2151 - DS2156
  • Application Note 2713: Switching Frame Mode In Live T1 Systems - DS2156
  • Application Note 2722: Interfacing the DS2156 Utopia II Bus to Dallas Demo Kits - DS2156
  • Application Note 2731: DS2155, DS21Q55, DS2156 Programming SLC-96 - DS2156, DS2156
  • Application Note 3121: Selecting a T1/E1/J1 Single-Chip Transceiver - DS2156
  • Application Note 3349: T1/E1 Loopback Operation for Dallas Semiconductor T1/E1/J1 transceivers - DS2156

    Evaluation Kits
  • DS2155DK, DS2156DK

    Design Guides
  • COMMUNICATIONS (PDF)

    Reliability Reports
  • Reliability Report: DS2156.pdf
  • Request Reliability Report for:

    Software/Models
  • DS2156 IBIS Model
  • DS2156LQFP BSDL Model
  • DS2156CSBGA BSDL Model
  • DS2156 Cadence Allegro Symbol
  • DS2156 Cadence Concept Symbol
  • DS2156 Logical Symbol-XML Format

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    2006-01-23
    This page last modified: 2007-07-31




             


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