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DS2156, DS2156L, DS2156LN
T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Industry's First T1/E1/J1 Transceiver for ATM Applications


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Status
Active: In Production.

Data Sheet
FULL DATA SHEET (PDF, 1.5MB)
Download this datasheet in PDF formatDownload   Send this datasheet to any email addressE-Mail


Errata
  • Errata DS2156 2156A2.pdf 
  • Description
    The DS2156 is a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and long-haul applications. The backplane is user-configurable for a TDM or UTOPIA II bus interface. The DS2156 is composed of a line interface unit (LIU), framer, HDLC controllers, and a UTOPIA/TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS2156 is pin and software compatible with the DS2155.

    The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line buildouts as well as CSU line buildouts of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock and data from the network.

    An evaluation kit is available:  DS2155DK, DS2156DK  

    Key Features   Applications/Uses
    • Complete T1/DS1/ISDN-PRI/J1 transceiver functionality
    • Complete E1 (CEPT) PCM-30/ISDN-PRI transceiver functionality
    • User-selectable TDM or UTOPIA II bus interface
    • Long-haul and short-haul line interface for clock/data recovery and waveshaping
    • CMI coder/decoder for optical I/F
    • Crystal-less jitter attenuator
    • Fully independent transmit and receive functionality
    • Dual HDLC controllers
    • Programmable BERT generator and detector
    • Internal software-selectable receive and transmit-side termination resistors for 75Ω/100Ω/120Ω T1 and E1 interfaces
    • Dual two-frame elastic-store slip buffers that connect to asynchronous backplanes up to 16.384MHz
    • 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output synthesized to recovered network clock
    • Additional features listed in full data sheet

     
  • Add/Drop Multiplexers
  • Inverse Mux ATM (IMA)
  • Routers/Switches
  • T1/E1/J1 Line Cards

    Key Specifications:  T/E Carrier & Packetized Products
    Part Number Transmission Standard Functions Channels In-to-Out Clocks
    (MHz)
    VSUPPLY
    (V)
    EV Kit Package/Pins Smallest Available Pckg.
    (mm2)
    Price
    max w/pins See Notes
    DS2156  T1/E1/J1 Framer + LIU 1 External Master Clock can be a multiple of 1.544 or 2.048 3.3 Yes
    CSBGA/100
    LQFP/100
    100 $18.00 @1k
    See All T/E Carrier & Packetized Products (102)

    Diagram
    DS2156, DS2156L, DS2156LN: Block Diagram
    Block Diagram

    Application Notes
  • Application Note 324: T1/E1 Network Interface Design - DS2156
  • Application Note 351: T1/E1 and T3/E3 Transformer Selection Guide - DS2156
  • Application Note 381: Interfacing the DS2155 to the MPC8260 - DS2156
  • Application Note 384: T1/E1/J1 Dual Connector Interface - DS2156
  • Application Note 389: DS2155 Internal BERT Programming - DS2156
  • Application Note 391: NRZ Applications - DS2156
  • Application Note 393: E1 Operation of Dallas Semiconductor Framers and SCTs - DS2156
  • Application Note 394: HDLC Configuration of Framers and Transceivers - DS2156
  • Application Note 405: Power-Fault Protection Layout - DS2156
  • Application Note 461: Programming and Controlling the FDL on DS2141A, DS2151 - DS2156
  • Application Note 2713: Switching Frame Mode In Live T1 Systems - DS2156
  • Application Note 2722: Interfacing the DS2156 Utopia II Bus to Dallas Demo Kits - DS2156
  • Application Note 2731: DS2155, DS21Q55, DS2156 Programming SLC-96 - DS2156, DS2156
  • Application Note 3121: Selecting a T1/E1/J1 Single-Chip Transceiver - DS2156
  • Application Note 3349: T1/E1 Loopback Operation for Dallas Semiconductor T1/E1/J1 transceivers - DS2156

    Evaluation Kits
  • DS2155DK, DS2156DK

    Design Guides
  • Communications (PDF)

    Reliability Reports
  • Reliability Report: DS2156.pdf
  • Request Reliability Report for:

    Software/Models
  • DS2156 IBIS Model
  • DS2156LQFP BSDL Model
  • DS2156CSBGA BSDL Model
  • DS2156 Cadence Allegro Symbol
  • DS2156 Cadence Concept Symbol
  • DS2156 Logical Symbol-XML Format

    Ordering Information
    Notes:

    1. Other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales.
    2. Didn't Find What You Need? Ask our applications engineers. Expert assistance in finding parts, usually within one business day.
    3. Part number suffixes: T or T&R = tape and reel;+ = RoHS/lead-free;# = RoHS/lead-exempt. More: SeeFull Data Sheet or Part Naming Conventions.
    4. * Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.


    Devices: 1-6 of 6

    DS2156 Free
    Sample
    Buy Status
    Package: TYPE PINS FOOTPRINT
      DRAWING CODE/VAR *
    Temp RoHS/Lead-Free?
    Materials Analysis
    DS2156G  
    Active CSBGA;100 pin;100 mm²
    Outline Drawing: 21-0357 (PDF)
    Land Pattern: 90-0332 (PDF)
    Use pkgcode/variation: X100-3*
    0°C to +70°C RoHS/Lead-Free: No
    Materials Analysis
    DS2156GN    
    Active CSBGA;100 pin;100 mm²
    Outline Drawing: 21-0357 (PDF)
    Land Pattern: 90-0332 (PDF)
    Use pkgcode/variation: X100-3*
    -40°C to +85°C RoHS/Lead-Free: No
    Materials Analysis
    DS2156L Free
    Sample
    Buy Status
    Package: TYPE PINS FOOTPRINT
      DRAWING CODE/VAR *
    Temp RoHS/Lead-Free?
    Materials Analysis
    DS2156L    
    Active LQFP;100 pin;262.4 mm²
    Outline Drawing: 21-0297 (PDF)
    Land Pattern: 90-0295 (PDF)
    Use pkgcode/variation: C100L-3*
    0°C to +70°C RoHS/Lead-Free: No
    Materials Analysis
    DS2156L+  
    Active LQFP;100 pin;262.4 mm²
    Outline Drawing: 21-0297 (PDF)
    Land Pattern: 90-0295 (PDF)
    Use pkgcode/variation: C100L+3*
    0°C to +70°C RoHS/Lead-Free: Lead Free
    Materials Analysis
    DS2156LN Free
    Sample
    Buy Status
    Package: TYPE PINS FOOTPRINT
      DRAWING CODE/VAR *
    Temp RoHS/Lead-Free?
    Materials Analysis
    DS2156LN    
    Active LQFP;100 pin;262.4 mm²
    Outline Drawing: 21-0297 (PDF)
    Land Pattern: 90-0295 (PDF)
    Use pkgcode/variation: C100L-3*
    -40°C to +85°C RoHS/Lead-Free: No
    Materials Analysis
    DS2156LN+  
    Active LQFP;100 pin;262.4 mm²
    Outline Drawing: 21-0297 (PDF)
    Land Pattern: 90-0295 (PDF)
    Use pkgcode/variation: C100L+3*
    -40°C to +85°C RoHS/Lead-Free: Lead Free
    Materials Analysis

    Notes and Comments
    The DS2156 connects directly to a UTOPIA II packetized backplane and performs the conversion between UTOPIA packet and TDM data streams. The backplane interface can be configured for UTOPIA II or TDM. The LIU and framer provide a true software-only configuration for connection to a T1, E1, or J1 line. The DS2156 conforms to all T1, E1, and J1 framing, synchronization, and transmission modes. It also supports all standard alarm generation and monitoring functions.

    Related Products
    DS21352, DS21552 3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers
    DS21354, DS21554 3.3V/5V E1 Single Chip Transceivers (SCT)

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    2006-01-23
    This page last modified: 2009-10-14


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