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MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and Data Driver


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Data Sheet
FULL DATA SHEET (PDF, 280kB)
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Description
The MAX9324 low-skew, low-jitter, clock and data driver distributes a differential LVPECL input to four differential LVPECL outputs and one single-ended LVCMOS output. All outputs default to logic low when the differential inputs equal GND or are left open. The MAX9324 operates from 3.0V to 3.6V, making it ideal for 3.3V systems, and consumes only 25mA (max) of supply current.

The MAX9324 features low 150ps (max) part-to-part skew, low 15ps output-to-output skew, and low 1.7ps RMS jitter, making the device ideal for clock and data distribution across a backplane or board. CLK_EN and SEOUT_Z control the status of the various outputs. Asserting CLK_EN low configures the differential (Q_, Q_) outputs to a differential low condition and SEOUT to a single-ended logic-low state. CLK_EN operation is synchronous with the CLK_ inputs. A logic high on SEOUT_Z places SEOUT in a high-impedance state. SEOUT_Z is asynchronous with the CLK (active-low CLK) inputs.

The MAX9324 is available in space-saving 20-pin TSSOP and ultra-small 20-pin 4mm x 4mm thin QFN packages and operates over the extended (-40°C to +85°C) temperature range.

Key Features   Applications/Uses
  • Differential Output-to-Output Skew
  • 1.7psRMS Added Random Jitter
  • 150ps (max) Part-to-Part Skew
  • 450ps Propagation Delay
  • Synchronous Output Enable/Disable
  • Single-Ended Monitor Output
  • Outputs Assert Low when CLK, active-low CLK are Open or at GND
  • 3.0V to 3.6V Supply Voltage Range
  • -40°C to +85°C Operating Temperature Range

 
  • Automated Test Equipment (ATE)
  • Central Office Backplane Clock Distribution
  • Data and Clock Driver and Buffer
  • DSLAM Backplane
  • Low-Jitter Data Repeater
  • Precision Clock Distribution
  • Wireless Base Stations

    Key Specifications:   High-Speed Interconnect (Differential Signaling)
    Part Number Features Rx Signal Type Tx Signal Type Functions Number of Rx Number of Tx Propagation Delay (max) (ps) Supply Voltage (V)
    MAX9324 
    Fail-Safe Inputs
    Synchronous Output Enable
    LVPECL CMOS
    LVPECL
    LVTTL
    Fan-Out Buffer
    1 5 600 3.3
    See All High-Speed Interconnect (Differential Signaling) (133)

    Diagram
    MAX9324: Typical Operating Circuit
    Typical Operating Circuit

    Evaluation Kits
    none

    Design Guides
  • INTERFACE (PDF)
  • FIBER (PDF)

    Reliability Reports
  • Show FIT data for:
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    Software/Models
  • MAX9324 IBIS Model

    Ordering Information
    Notes:

    1. Other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales.
    2. Didn't Find What You Need? Ask our applications engineers. Expert assistance in finding parts, usually within one business day.
    3. Part number suffixes: T or T&R = tape and reel; + = RoHS/lead-free; # = RoHS/lead-exempt. More: SeeFull Data Sheet or Part Naming Conventions.
    4. * Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.


    Devices: 1-4 of 4

    MAX9324 Free
    Sample
    Buy
    Package: TYPE PINS FOOTPRINT
      DRAWING CODE/VAR *
    Temp RoHS/Lead-Free?
    Materials Analysis
    MAX9324EUP  
    TSSOP;20 pin;
    Dwg: 21-0066 (PDF)
    Use pkgcode/variation: U20-3*
    -40°C to +85°C RoHS/Lead-Free: No
    Materials Analysis
    MAX9324EUP-T  
    TSSOP;20 pin;
    Dwg: 21-0066 (PDF)
    Use pkgcode/variation: U20-3*
    -40°C to +85°C RoHS/Lead-Free: No
    Materials Analysis
    MAX9324EUP+  
    TSSOP;20 pin;
    Dwg: 21-0066 (PDF)
    Use pkgcode/variation: U20+3*
    -40°C to +85°C RoHS/Lead-Free: Lead Free
    Materials Analysis
    MAX9324EUP+T  
    TSSOP;20 pin;
    Dwg: 21-0066 (PDF)
    Use pkgcode/variation: U20+3*
    -40°C to +85°C RoHS/Lead-Free: Lead Free
    Materials Analysis

    Related Products
    MAX9315 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver
    MAX9316 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver
    MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver
    MAX9326 1:9 Differential LVPECL/LVECL/HSTL Clock and Data Driver
    MAX9311, MAX9313 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
    MAX9312, MAX9314 Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

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     Description 
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    Document Ref.: 19-2576; Rev 0; 2002-10-31
    This page last modified: 2007-07-17



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