One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver
1:4, LVCMOS-to-LVPECL, Low-Skew, Low-Jitter, Output Clock and Data Driver Distributes One of Two Single-Ended LVCMOS Inputs to Four Differential LVPECL Outputs
The MAX9323 low-skew, low-jitter, clock and data driver distributes one of two single-ended LVCMOS inputs to four differential LVPECL outputs. A single logic control signal (CLK_SEL) selects the input signal to distribute to all outputs. The device operates from 3.0V to 3.6V, making the device ideal for 3.3V systems, and consumes only 25mA (max) of supply current.
The MAX9323 features low 150ps part-to-part skew, low 11ps output-to-output skew, and low 1.7ps RMS jitter, making the device ideal for clock and data distribution across a backplane or board. All outputs are enabled and disabled synchronously with the clock input to prevent partial output clock pulses.
The MAX9323 is available in space-saving 20-pin TSSOP and ultra-small 20-pin 4mm x 4mm thin QFN packages and operates over the extended (-40°C to +85°C) temperature range. The MAX9323 is pin compatible with Integrated Circuit Systems' ICS8535-01.
Key Features
Applications/Uses
1.7psRMS Added Random Jitter
150ps (max) Part-to-Part Skew
11ps Output-to-Output Skew
450ps Propagation Delay
Pin Compatible with ICS8535-01
Consumes Only 25mA (max) Supply Current
(50% Less than ICS8535-01)
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