The MAX9384 fully differential dual 2:1 multiplexer (mux) features extremely low propagation delay (560ps max) and output-to-output skew (40ps max). The device is ideal for clock and data multiplexing applications. The two 2:1 muxes are controlled individually or simultaneously through mux select inputs COM_SEL, SEL0, and SEL1. The mux select inputs are compatible with ECL/PECL logic, and are referenced to on-chip outputs VBB0 and VBB1, nominally VCC - 1.33V.
The differential inputs D, D-bar can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip supply output VBB as a reference voltage. All the differential inputs have bias and clamp circuits that force the outputs to a low default when the inputs are left open or at VEE. The single-ended mux select inputs have pulldowns to VEE, providing low default inputs when the select inputs are left open.
The device operates with a wide supply range (VCC - VEE) of +3.0V to +5.5V for PECL or -3.0V to -5.5V for ECL, and is pin compatible with the MC100LVEL56 and MC100EL56. The MAX9384 is offered in a 20-pin wide SO package, and is specified for operation from -40°C to +85°C.
Key Features
Applications/Uses
40psP-P Deterministic Jitter
440ps Differential Propagation Delay
12ps Output-to-Output Skew
Individual and Common Select
+3.0V to +5.5V Supplies for Differential LVPECL/PECL
-3.0V to -5.5V Supplies for Differential LVECL/ECL
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
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MAX9384
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MAX9384EWP
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SOIC(W);20 pin;137.3 mm²
Outline Drawing: 21-0042 (PDF)
Land Pattern: 90-0108 (PDF)
Use pkgcode/variation: W20-1*
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