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Maxim > Products > Interface and Interconnect  Optoelectronics  Timekeeping, Timers, and Counters  Clock Distribution 
MAX9322
LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver

1:15 Divide-by-1, Divide-by-2 Differential LVPECL Clock Driver


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Description
FULL DATA SHEET (PDF, 196kB)
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The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from one of two input clocks with input switching frequency in excess of 1.0GHz. The 15 outputs are arranged in four banks with 2, 3, 4, and 6 outputs, respectively. Each output bank is individually programmable to provide a divide-by-1 or divide-by-2 frequency function.

The MAX9322 operates in LVPECL systems with a +2.375V to +3.8V supply or in LVECL systems with a -2.375V to -3.8V supply. A VBB reference output provides compatibility with single-ended clock input signals and a master reset input provides a simultaneous reset on all outputs.

The MAX9322 is available in 52-pin TQFP and 68-pin QFN packages and is specified for operation over -40°C to +85°C. For 1:10 clock drivers, refer to the MAX9311/MAX9313 data sheet. For 1:5 clock drivers, refer to the MAX9316 data sheet.

Key Features   Applications/Uses
  • 1.2ps (RMS) Maximum Random Jitter
  • 300mV Differential Output at 1.0GHz
  • 900ps Propagation Delay
  • Selectable Divide-by-1 or Divide-by-2 Frequency Outputs
  • Multiplexed 2:1 Input Function
  • LVECL Operation from VEE = -2.375V to -3.8V
  • LVPECL Operation from VCC = +2.375V to +3.8V
  • ESD Protection: > 2kV Human Body Model

 
  		• Automated Test Equipment (ATE)
  		• Central Office Backplane Clock Distribution
  		• DSLAM Backplane
  		• Low-Jitter Data Repeater
  		• Precision Clock Distribution
  		• Wireless Base Stations

    Key Specifications:   High-Speed Interconnect (Differential Signaling)
    Part Number Features Rx Signal Type Tx Signal Type Functions Number of Rx Number of Tx Propagation Delay (max) (ps) Supply Voltage (V) Random Jitter (max) (ps RMS) Deterministic Jitter (max) (ps pp) Channel-to-Channel Skew (max) (ps) Output Transition Time (max) (ps) ESD Protection (±kV) RoHS Available Package Smallest Available Package (max w/pins) (mm2)
    MAX9322 
    •Differential Input Mux
    •Divide-by-1 or Divide-by-2 Outputs
    		 HSTL
    LVECL
    LVPECL     		LVECL
    LVPECL
    •Fan-Out Buffer
    		 2 15 1225 3.3 1.2 60 85 400 2 Yes LQFP/52 149
    See All High-Speed Interconnect (Differential Signaling) (131)

    Diagram
    MAX9322: Typical Operating Circuit
    Typical Operating Circuit

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    Document Ref.: 19-2544; Rev 2; 2007-02-16
    This page last modified: 2007-07-13




             


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