- LVDS or LVTTL/LVCMOS Input Selection
- LVDS Input Fail-Safe Sets Outputs High for Open, Undriven Short, or Undriven Parallel Termination
- Two Output Banks with Separate Bank Enables
- Integrated Output Series Termination for 60Ω Lines
- 200ps (max) Output-to-Output Skew
- ±100ps (max) Peak-to-Peak Added Output Jitter
- 42% to 58% Output Duty Cycle at 125MHz
- Guaranteed 125MHz Operating Frequency
- LVDS Input Is High Impedance with VCC = 0V
or Open (Hot Swappable)
- 28-Pin Exposed- and Nonexposed-Pad TSSOP
or 32-Lead QFN Packages
- -40°C to +85°C Operating Temperature
- 3.0V to 3.6V Supply Voltage
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