The MAX3892 serializer is ideal for converting 4-bit-wide,
622Mbps parallel data to 2.5Gbps serial data in
DWDM and SONET/SDH applications. A 4 x 4-bit FIFO
allows for any static delay between the parallel output
clock and parallel input clock. Delay variation up to a
unit interval (UI) is allowed after reset. A fully integrated
phase-locked loop (PLL) synthesizes an internal
2.5GHz serial clock from a 622MHz, 155.5MHz,
77.8MHz, or 38.9MHz reference clock. A selectable
dual VCO allows excellent jitter performance at both
SONET and forward-error correction (FEC) data rates.
Operating from a single 3.3V supply, this device
accepts low-voltage differential-signal (LVDS) clock and
data inputs for interfacing with high-speed digital circuitry,
and delivers current-mode logic (CML) serial data
and clock outputs. A loopback data output is provided
to facilitate system diagnostic testing. The MAX3892 is
available in the extended temperature range (-40°C to
+85°C) in 44-pin QFN and TQFN packages.
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
Devices:
1-4 of 4
MAX3892
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Status
Package:
TYPE PINS FOOTPRINT
DRAWING CODE/VAR *
Temp
RoHS/Lead-Free? Materials Analysis
MAX3892EGH-D
Active
QFN;44 pin;50 mm²
Outline Drawing: 21-0092 (PDF)
Land Pattern: 90-0223 (PDF)
Use pkgcode/variation: G4477-3*
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