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MAX5306, MAX5307
Low-Power, Low-Glitch, Octal 12-Bit Voltage-Output DACs with Serial Interface


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Status
Active: In Production.

Description
FULL DATA SHEET (PDF, 288kB)
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The MAX5306/MAX5307 are 12-bit, eight channel, low-power, voltage-output, digital-to-analog converters (DACs) in a space-saving 16-pin TSSOP package. The wide +2.7V to +5.5V supply voltage range and less than 215µA (max) supply current per DAC are excellent for low-power and low-voltage applications. The low 2nV/s glitch energy of the MAX5306/MAX5307 makes them ideal for digital control of fast-response, closed-loop systems.

The MAX5306 has a digital output (DOUT) that can be used for daisy-chaining multiple devices. The MAX5307 has a hardware reset input (active-low CLR) which clears all registers and DACs to zero. The MAX5306/MAX5307 have a software shutdown feature that reduces the supply current to 1µA. The MAX5306/MAX5307 feature a load DAC (active-low LDAC) function that updates the output of all eight DACs simultaneously. The 3-wire SPI™, QSPI™, MICROWIRE™ and DSP-compatible serial interface allows the input and DAC registers to be updated independently or simultaneously with a single software command. These devices use a double-buffered design to minimize the digital-noise feedthrough from the digital inputs to the outputs.The MAX5306/MAX5307 operating temperature range is from -40°C to +85°C.

Key Features   Applications/Uses
  • Eight Highly Integrated 12-Bit DACs in 16-Pin TSSOP (6.4mm x 5mm) Package
  • Ultra-Low Glitch Energy < 2nV/s
  • Low Total Supply Current:
    • 1.7mA (max) with VREF = VDD = +5.5V
  • +2.7V to +5.5V Wide Single-Supply Range
  • Fast 5µs Settling Time
  • Software-Selectable Shutdown Mode < 1µA
  • 15MHz 3-Wire SPI, QSPI, and MICROWIRE-Compatible Serial Interface
  • Power-Up Reset to Zero Scale

 
  • Control of Optical Components
  • Gain and Offset Adjustment
  • Portable Instrumentation Equipment
  • Power Amplifier Control
  • Process-Control I/O Boards

    Diagram
    MAX5306, MAX5307: Functional Block Diagram
    Functional Block Diagram

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    Document Ref.: 19-2132; Rev 0; 2001-08-24
    This page last modified: 2008-10-31


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