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MAX9320, MAX9320A
1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers


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Status
Active: In Production.

Description
FULL DATA SHEET (PDF, 624kB)
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The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage.

The MAX9320/MAX9320A feature ultra-low propagation delay (208ps), part-to-part skew (20ps), and output-to-output skew (6ps) with 30mA maximum supply current, making these devices ideal for clock distribution. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply.

The pinout is the only difference between the MAX9320 and MAX9320A. Multiple pinouts are provided to simplify routing across a backplane to either side of a double-sided board.

These devices are offered in space-saving 8-pin SOT23, µMAX®, and SO packages.

Key Features   Applications/Uses
  • Improved Second Source of the MC10LVEP11 (MAX9320)
  • +2.25V to +3.8V Differential HSTL/LVPECL Operation
  • -2.25V to -3.8V LVECL Operation
  • Low 22mA (typ) Supply Current
  • 20ps (typ) Part-to-Part Skew
  • 6ps (typ) Output-to-Output Skew
  • 208ps (typ) Propagation Delay
  • Minimum 300mV Output at 3GHz
  • Outputs Low for Open Input
  • ESD Protection >2kV (Human Body Model)
  • Available in Thermally Enhanced Exposed-Pad SO Package

 
  • Low-Jitter Data Repeater
  • Precision Clock Distribution
  • Protection Switching

    Key Specifications:  High-Speed Interconnect (Differential Signaling)
    Part Number Features Signal Type Signal Type Functions Rx Tx tPD
    (ps)
    VSUPPLY
    (V)
    Price
    Rx Tx max See Notes
    MAX9320  Fail-Safe Inputs
    HSTL
    LVECL
    LVPECL
    LVECL
    LVPECL
    Fan-Out Buffer 1 2 270 3.3 $3.44 @1k
    MAX9320A  -
    See All High-Speed Interconnect (Differential Signaling) (132)

    Diagram
    MAX9320, MAX9320A: Pin Configuration
    Pin Configuration

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    Document Ref.: 19-2201; Rev 3; 2004-11-12
    This page last modified: 2009-10-27


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