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DS21352, DS21552
3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers


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Status
Active: In Production.

Description
FULL DATA SHEET (PDF, 1.1MB)
Download this datasheet in PDF formatDownload   Send this datasheet to any email addressE-Mail
The DS21352/552 T1 single chip transceiver contains all of the necessary functions for connection to T1 lines whether they are DS1 long haul or DSX-1 short haul. The clock recovery circuitry automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX-1 line build outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of internal registers which the user can access and control the operation of the unit. Quick access via the parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12-90), AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.

An evaluation kit is available:  DS21352DK  

Key Features
  • Complete DS1/ISDN-PRI/J1 transceiver functionality
  • Long and Short haul LIU
  • Crystal-less jitter attenuator
  • Generates DSX-1 and CSU line build-outs
  • HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation
  • Dual two-frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192MHz
  • 8.192MHz clock output locked to RCLK
  • Interleaving PCM Bus Operation
  • Per-channel loopback and idle code insertion
  • 8-bit parallel control port muxed or nonmuxed buses (Intel or Motorola)
  • Programmable output clocks for Fractional T1
  • Fully independent transmit and receive functionality
  • Generates/detects in-band loop codes from 1 to 8 bits in length including CSU loop codes
  • IEEE 1149.1 JTAG-Boundary Scan
  • Pin compatible with DS2152/54/354/554 SCTs
  • 100-pin LQFP package (14 mm x 14 mm) 3.3V (DS21352) or 5V (DS21552) supply; low power CMOS

Key Specifications:  T/E Carrier & Packetized Products
Part Number Transmission Standard Functions Channels VSUPPLY
(V)
Package/Pins Smallest Available Pckg.
(mm2)
Price
max w/pins See Notes
DS21352  T1/J1 Framer + LIU 1 3.3
CSBGA/100
LQFP/100
100 $16.00 @1k
DS21552  5
LQFP/100
262.4 $16.00 @1k
See All T/E Carrier & Packetized Products (102)

Diagram
DS21352, DS21552: Pin Assignment
Pin Assignment

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    2000-12-07
    This page last modified: 2009-10-28


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