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DS1WM
Synthesizable 1-Wire Bus Master


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Status
Active: In Production.

Data Sheet
FULL DATA SHEET (PDF, 124kB)
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Description
As more 1-Wire® devices become available, more and more users have to deal with the demands of generating 1-Wire signals to communicate to them. This usually requires "bit-banging" a port pin on a microprocessor, and having the microprocessor perform the timing functions required for the 1-Wire protocol. While 1-Wire transmission can be interrupted mid-byte, it cannot be interrupted during the "low" time of a bit time slot; this means that a CPU will be idled for up to 60 microseconds for each bit sent and at least 480 microseconds when generating a 1-Wire reset. The 1-Wire Master helps users handle communication to 1-Wire devices in their system without tying up valuable CPU cycles. Integrated into a user's ASIC as a 1-Wire port, the Verilog or VHDL core uses little chip area (3470 gates plus 2 bond pads).

This circuit is designed to be memory mapped into the user's system and provides complete control of the 1-Wire bus through 8-bit or single commands. The host CPU loads commands, reads and writes data, and sets interrupt control through six individual registers. All of the timing and control of the 1-Wire bus are generated within. The host merely needs to load a command or data and then may go on about its business. When bus activity has generated a response that the CPU needs to receive, the 1-Wire Master sets a status bit and, if enabled, generates an interrupt to the CPU. In addition to write and read simplification, the 1-Wire Master also provides a Search ROM Accelerator function relieving the CPU from having to perform the complex single-bit operations on the 1-Wire bus.

Key Features
  • Memory maps into any standard byte-wide data bus.
  • Eliminates CPU "bit-banging" by internally generating all 1-Wire timing and control signals.
  • Generates interrupts to provide for more efficient programming.
  • Search ROM Accelerator relieves CPU from any single bit operations on the 1-Wire Bus.
  • Capable of running off any system clock from 4MHz to 128MHz.
  • Small size: all digital design, only 3470 gates.
  • Applications include any circuit containing a 1-Wire communication bus.
  • Supports standard and overdrive 1-Wire communication speeds
  • Supports strong pull-up specifications.
  • Master available in both Verilog and VHDL
  • Supports single bit transmissions.
  • Provides added support for long line conditions.

Key Specifications:  1-Wire Interface Products
Part Number Functions Features Package/Pins
DS1WM  Bus Master Macro Verilog/VHDL macro for ASIC 1-Wire® bus master
See Data Sheet/
See All 1-Wire Interface Products (5)

Diagram
DS1WM: Block Diagram
Block Diagram

Application Notes
  • Application Note 119: Embedding the 1-Wire® Master in FPGAs or ASICs - DS1WM
  • Application Note 120: Using an API to Control the DS1WM 1-Wire® Bus Master - DS1WM
  • Application Note 145: Interfacing the 1-Wire Master (DS1WM) to an ARM7 Processor - DS1WM
  • Application Note 214: Using a UART to Implement a 1-Wire Bus Master - DS1WM

    Design Guides
  • 1-Wire® Products (PDF)

    Reliability Reports
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    Software/Models
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    Ordering Information
    Notes:

    1. Other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales.
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    3. Part number suffixes: T or T&R = tape and reel;+ = RoHS/lead-free;# = RoHS/lead-exempt. More: SeeFull Data Sheet or Part Naming Conventions.
    4. * Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.


    This product cannot be purchased through our web site. Contact factory for availability.


    More Information
  • 1-Wire Support: http://support.maxim-ic.com/1-wire

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    2007-09-18
    This page last modified: 2009-10-23


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