The DS1013 3-in-1 Silicon Delay Lines provide three independent delay elements that reproduce logic inputs after delays ranging from 10ns to 200ns at each output. Both leading- and trailing-edge accuracy are specified. Delay tolerances are ±2ns for delays of 10ns to 60ns; ±3% for delays of 70ns to 100ns, and ±5% for delays over 150ns. Each output can drive up to ten 74LS loads.
By enabling precise timing adjustments, Dallas Silicon Delay Lines improve system performance. They provide an effective, economical solution to the designer working with the complex timing requirements of mismatched ASICs or other components, or with the strict timing tolerances of increasing system clock rates. Each delay line die is laser-optimized and molded into an auto-insertable DIP or space-saving SOIC package.
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
Download
E-Mail