The DS1010 10-in-1 Silicon Delay Line reproduces an input logic state at the output after delays provided by 10 equally spaced taps. Delays range from 5ns to 500ns (see table), with a tolerance of ±2ns or 5% (whichever is greater) at room temperature.
By enabling precise timing adjustments, Dallas Silicon Delay Lines improve system performance. They provide an effective, economical solution to the designer working with the complex timing requirements of mismatched ASICs or other components, or with the strict timing tolerances of increasing system clock rates. Each delay line die is laser-optimized and molded into an auto-insertable DIP or space-saving SOIC package.
Key Features
All-silicon timed delay circuit
10 equally spaced taps
Delay tolerance ±2ns or 5%, whichever is greater
Stable, precise delays; leading and trailing edge accuracy
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
Devices:
1-54
of
54
DS1010
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TYPE PINS FOOTPRINT
DRAWING CODE/VAR *
Temp
RoHS/Lead-Free? Materials Analysis
DS1010C-402
PDIP;14 pin;158 mm²
Dwg: 56-G5005-001A (PDF)
Use pkgcode/variation: P14-4*
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